A pinboard by
Seyedbehzad Naderi

Seyed Behzad Naderi (S'10) received the B.S. and M.Sc. degrees in power engineering from the University of Tabriz, Tabriz, Iran, in 2008 and 2011, respectively. He is currently PhD Fellow at the School of Engineering and ICT, University of Tasmania, Australia and working with Prof Michael Negnevitsky. Meanwhile, he was also with Department of Energy Technology as a guest visiting PhD student at Aalborg University, Denmark and cooperating with Prof Frede Blaabjerg. He is the author and coauthor of more than 20 journal and conference papers. His current research interests include fault current limiters, power system transient stability, power quality, flexible ac transmission systems, and renewable energy.

Renewable Energy, Wind Turbine, Power Electronics, Power System Analysis, Transient Stability, Fault Current Limiters, Power Quality


Efficient fault ride-through scheme for three phase voltage source inverter-interfaced (DG)

This research proposes a DC link adjustable resistive type fault current limiter (AR-FCL) based-voltage source inverter (VSI) fault ride-through (FRT) capability improvement, which is new approach of using FCLs. Instead of using three phase FCLs in AC side of the VSI, just one single phase proposed AR-FCL is connected in series with DC side of the VSI. During normal operation, the AR-FCL does not have effect on the VSI performance. When fault happens, the AR-FCL limits AC side fault currents in faulty phases to safe area operation of semiconductor devices of inverter, and does not affect healthy lines. The desired limited fault current value can be achieved by discharging and charging of DC inductor using large resistance, which enters and retreats by turning off and on of the AR-FCL's semiconductor switch, respectively. The VSI does not require to change its control strategy from normal to fault mode operation. Consequently, wind-up and latch-up problems are smoothed. Analytical analysis is provided in each switching interval to highlight effectiveness of the AR-FCL on the VSI fault current limitation. The proposed FRT scheme is validated through both extensive simulation studies in PSCAD/EMTDC environment and three-phase experimental prototype for all symmetrical, asymmetrical, and transient faults.