PhD Scholar, Indian Institute of Technology Kharagpur
A protocol to provide proofs of sensor data using unreliability of Physically Unclonable Functions
The Internet of Things (IoT) is envisaged to consist of billions of connected devices. These devices are often coupled with sensors which generate huge volumes of data enabling control-and-command in the IoT paradigm. However, integrity of this data is of utmost concern for securing the IoT, and is promisingly addressed leveraging the inherent unreliability of Physically Unclonable Functions (PUFs) w.r.t. ambient parameter variations, using the concept of Virtual Proofs (VPs). These proto- cols do not use explicit keys and aim at proving the authenticity of the sensor information from alterations by adversaries. However, a key observation is that the existing protocols do not use the sensor data as the challenge of the PUFs. The resultant protocols have often a often allow only a limited number of authentication attempts, and require linear search in the verifier database rendering them unsuitable for IoTs. To alleviate these issues we develop a new class of protocols here the sensor data is used as a part of the challenge space. This approach brings forth several challenges related to the application of the sensor data in the PUF to ensure that changes in the sensor values have a high sensitivity on the overall PUF response. We illustrate through actual experiments with FPGA PUFs designed using the Double Arbiter PUF (DAPUF) architecture which are implemented with superior uniformity, uniqueness, and reliability on Xilinx Artix-7 FPGAs. Without loss of generality, we develop the protocol to authenticate sensor data against temperature variation. In the security analysis, we have shown that how the unreliability of the responses across the temperature variation can be utilized to prove the trustworthiness of the sensed data. We show that the protocol on such PUF designs can be effectively used to authenticate wide variations of temperature from -20 ◦ C to 80 ◦ C.
Abstract: Various embodiments of the invention allow to take advantage of the natural statistical variation of physical properties in a semiconductor device in order to create truly random, repeatable, and hard to detect cryptographic bits. In certain embodiments, this is accomplished by pairing mismatch values of PUF elements so as to ensure that PUF key bits generated thereform remain insensitive to environmental errors, without affecting the utilization rate of available PUF elements.
Pub.: 01 Nov '16, Pinned: 15 Nov '17
Abstract: An identity card, comprising a card body and a physical unclonable function are arranged within the card body, wherein the physical unclonable function comprises a first light influencing layer and a second light influencing layer.
Pub.: 15 Nov '16, Pinned: 15 Nov '17
Abstract: Physically unclonable functions (PUFs) have been touted for their inherent resistance to invasive attacks and low cost in providing a hardware root of trust for various security applications. SRAM PUFs in particular are popular in industry for key/ID generation. Due to intrinsic process variations, SRAM cells, ideally, tend to have the same start-up behavior. SRAM PUFs exploit this start-up behavior. Unfortunately, not all SRAM cells exhibit reliable start-up behavior due to noise susceptibility. Hence, design enhancements are needed for improving reliability. Some of the proposed enhancements in literature include fuzzy extraction, error-correcting codes and voting mechanisms. All enhancements involve a trade-off between area/power/performance overhead and PUF reliability. This paper presents a design enhancement technique for reliability that improves upon previous solutions. We present simulation results to quantify improvement in SRAM PUF reliability and efficiency. The proposed technique is shown to generate a 128-bit key in ≤0.2 μ s at an area estimate of 4538 μ m 2 with error rate as low as 10 − 6 for intrinsic error probability of 15%.
Pub.: 12 Jan '17, Pinned: 15 Nov '17
Abstract: Some implementations disclosed herein provide techniques and arrangements for provisioning keys to integrated circuits/processors. A processor may include physically unclonable functions component, which may generate a unique hardware key based at least on at least one physical characteristic of the processor. The hardware key may be employed in encrypting a key such as a secret key. The encrypted key may be stored in a memory of the processor. The encrypted key may be validated. The integrity of the key may be protected by communicatively isolating at least one component of the processor.
Pub.: 10 Jan '17, Pinned: 15 Nov '17
Abstract: State-of-the-art technology for pulse counter electronics offers an important range of commercial devices, but such systems are usually expensive due to the complex logic used for this task. The use of counting electronics in conjunction with photon counters can be used, for example, to perform experimental tests in Quantum Optics and Quantum Information Science. Here, we present the development and implementation of a low cost module for multiphoton coincidence statistics with detection windows of a few nanoseconds. The module consists of an array of logic gates, with a frequency operation of 250 MHz that corrects and amplifies the detectors signal. The device characterisation was done by means of detection of Transistor-Transistor Logic (TTL) signals retrieved from a signal generator, and implemented in an optical setup. The detected output signals (TTL pulses) were analysed and stored in a computer by means of a Field Programmable Gate Array (FPGA). Our module incorporates fundamental electronics that is currently used in the first experimental proof-of-principle tests in quantum information and molecular spectroscopy at CIBioFi.
Pub.: 15 Jun '17, Pinned: 15 Nov '17