Graph Theory in Analog Synthesis Methodology

CURATOR

A pinboard by

MOUSUMI BHANJA

PINBOARD SUMMARY

Synthesis of analog circuits using graph theory is very useful to develop analog CAD or EDA tool

Design and synthesis methodology of digital system is equipped with cell based design techniques like PLD, CPLD, FPGA etc., which provide reusability and programmability. Synthesis of analog circuits still lacks a proper procedure in a hierarchical manner. Graph theory is an efficient way to represent circuit network.

60 ITEMS PINNED

An Efficient Reconfigurable FIR Digital Filter Using Modified Distribute Arithmetic Technique

Abstract: This paper provides modified Distributed Arithmetic based technique to compute sum of products saving appreciable number of Multiply And accumulation blocks and this consecutively reduces circuit size. In this technique multiplexer based structure is used to reuse the blocks so as to reduce the required memory locations. In this technique a Carry Look Ahead based adder tree is used to have better area-delay product. Designing of FIR filter is done using VHDL and synthesized using Xilinx 12.2 synthesis tool and ISIM simulator. The power analysis is done using Xilinx Xpower analyzer. The proposed structure requires nearly 42% less cells, 40% less LUT flip-flop pairs used, and also 2% less power compared with existing structure.

Pub.: 27 Apr '17, Pinned: 26 Aug '17

Synthesis of Data Completion Scripts using Finite Tree Automata

Abstract: In application domains that store data in a tabular format, a common task is to fill the values of some cells using values stored in other cells. For instance, such data completion tasks arise in the context of missing value imputation in data science and derived data computation in spreadsheets and relational databases. Unfortunately, end-users and data scientists typically struggle with many data completion tasks that require non-trivial programming expertise. This paper presents a synthesis technique for automating data completion tasks using programming-by-example (PBE) and a very lightweight sketching approach. Given a formula sketch (e.g., AVG($?_1$, $?_2$)) and a few input-output examples for each hole, our technique synthesizes a program to automate the desired data completion task. Towards this goal, we propose a domain-specific language (DSL) that combines spatial and relational reasoning over tabular data and a novel synthesis algorithm that can generate DSL programs that are consistent with the input-output examples. The key technical novelty of our approach is a new version space learning algorithm that is based on finite tree automata (FTA). The use of FTAs in the learning algorithm leads to a more compact representation that allows more sharing between programs that are consistent with the examples. We have implemented the proposed approach in a tool called DACE and evaluate it on 84 benchmarks taken from online help forums. We also illustrate the advantages of our approach by comparing our technique against two existing synthesizers, namely PROSE and SKETCH.

Pub.: 05 Jul '17, Pinned: 26 Aug '17

Minimum parasitic effects biquadratic OTA-C filter architectures

Abstract: This paper presents a systematic analysis to determine the tuning range limitations of biquadratic OTAC filter architectures, as well as a strategy for the selection of minimum parasitic effects filter structures for a given transfer function (filter type). The analysis uses an OTA macromodel that includes finite input and output impedances along with frequency-dependent transconductance. Experimental data of the macromodel parameters of real OTAs along with analytical results are used to estimate the practical tuning (bounds) limitations of the different biquadratic filter structures. Some of the available transfer functions from these filter architectures present minimum parasitic effects. Experimental results from CMOS chip tests showed agreement with the minimum parasitic effects theoretical results.

Pub.: 01 Dec '91, Pinned: 26 Aug '17

A 7.2 GHz bipolar operational transconductance amplifier for fully integrated OTA-C filters

Abstract: Using a complementary bipolar junction transistor process having NPN transistors with a maximum short circuit common emitter gain-bandwidth product (ft) of 7.2 GHz and PNP transistors with a maximumft of 4.5 GHz, an operational transconductance amplifier has been designed for a 3-dB bandwidth of 7.2 GHz. The design process invokes new phase compensation strategies and develops innovative new ways of exploiting existing broadbanding techniques. The utility of the design is confirmed by demonstrating its application in two operational transconductance amplifier-capacitance filters. One of these examples is a 225 MHz lowpass filter, while the other is a bandpass filter with a center frequency of 250 MHz.

Pub.: 01 Nov '94, Pinned: 26 Aug '17

A Low-Power 3V Lowpass OTA-C Filter for Megahertz Range

Abstract: By applying a signal-flow graph (SFG) based filter synthesis an active OTA-C topology for integration of a 5-degree elliptic lowpass (LP) filter has been designed. The dynamic range has been maximized for this single-ended OTA-C filter, which has floating capacitors. This has been done through the use of an optimizing circuit simulator. Thus low-voltage (3V) operation despite high signal amplitudes (1Vpp) has been achieved. A linearized operational transconductance amplifier (OTA) has been designed and optimized for the filter. For comparison purposes the single-ended design has been converted to a fully differential one with an additional +6dB of gain. Integrated filters realized with a 1.2 μm CMOS process have been thoroughly measured. The filters are especially applicable for mobile communications because of low power consumption.

Pub.: 01 Jan '97, Pinned: 26 Aug '17

A CMOS Continuous-Time Low-Pass Notch Filter for EEG Systems

Abstract: A CMOS OTA-C low-pass notch filter for EEG application is described. The pass-band covers four bands of brain wave and provides more than 65 dB attenuation for the 50 Hz power line interference. The OTA works in the weak inversion region and a low transconductance of 3 nA/V is achieved. The low transconductance enables using small capacitors in the OTA-C filter so that the filter is suitable for the multi-channel EEG integrated circuits. The measured results show the good performance of the filter for filtering the noise in acquired EEG signals.

Pub.: 01 Sep '05, Pinned: 26 Aug '17

Filter circuit

Abstract: An R-2R resistor circuit network 12 used in a filter circuit according to the present invention has a path through which each branch current flows to a next integrating capacitor and a path through which each branch current flows to a low impedance analog midpoint (ground potential) Vss. The path can be selected by digital control bit data Bn to B0 for each branch current. By this, a frequency characteristic of a filter using an integrator as a component may be changed with an accuracy of (n+1)(Gm1)/Cf from (n+1)(Gm1)/Cf to ((2n+1n+1)(Gm1)Cf. As a result, by setting the setting bit width to 7 (n=6), a variable range of the frequency characteristic of over one hundredfold may be easily realized.

Pub.: 03 Jul '07, Pinned: 26 Aug '17

Tunable mixed-mode OTA-C universal filter

Abstract: A novel electronically tunable mixed-mode universal biquad by using four single-output and one dual-output-operational transconductance amplifiers, two grounded capacitors is proposed. The proposed circuit has ability to realize voltage, current, transconductance, and transresistance mode, and can the following advantageous features: (i) realization of low-pass, band-pass, high-pass, notch, and all-pass filter responses from the same configuration, (ii) employment of only grounded capacitors ideal for integrated circuit implementation, (iii) orthogonal controlling of ωo and Q for easily electronic tunability, and (iv) low active and passive sensitivity performance. Finally, to verify our architecture, we have designed this analog filter chip with TSMC 0.35-μm 2P4M CMOS technology. This chip operates to 1 MHz and consumes 30.95 mW. The chip area of the analog filter is about 0.823 mm2.

Pub.: 04 Nov '08, Pinned: 26 Aug '17

Low-power signal processing devices for portable ECG detection.

Abstract: An analog front end for diagnosing and monitoring the behavior of the heart is presented. This sensing front end has two low-power processing devices, including a 5(th)-order Butterworth operational transconductance-C (OTA-C) filter and an 8-bit successive approximation analog-to-digital converter (SAADC). The components fabricated in a 0.18-microm CMOS technology feature with power consumptions of 453 nW (filter) and 940 nW (ADC) at a supply voltage of 1 V, respectively. The system specifications in terms of output noise and linearity associated with the two integrated circuits are described in this paper.

Pub.: 24 Jan '09, Pinned: 26 Aug '17

Systematic Design and Modeling of a OTA-C Filter for Portable ECG Detection.

Abstract: This study presents a systematic design of the fully differential operational transconductance amplifier-C (OTA-C) filter for a heart activities detection apparatus. Since the linearity and noise of the filter is dependent on the building cell, a precise behavioral model for the real OTA circuit is created. To reduce the influence of coefficient sensitivity and maintain an undistorted biosignal, a fifth-order ladder-type lowpass Butterworth is employed. Based on this topology, a chip fabricated in a 0.18- mum CMOS process is simulated and measured to validate the system estimation. Since the battery life and the integration with the low-voltage digital processor are the most critical requirement for the portable diagnosis device, the OTA-based circuit is operated in the subthreshold region to save power under the supply voltage of 1V. Measurement results show that this low-voltage and low-power filter possesses the HD3 of -48.9 dB, dynamic range (DR) of 50 dB, and power consumption of 453 nW. Therefore, the OTA-C filter can be adopted to eliminate the out-of-band interference of the electrocardiogram (ECG) whose signal bandwidth is located within 250 Hz.

Pub.: 01 Feb '09, Pinned: 26 Aug '17

Trade-offs in the OTA-based analog filter design

Abstract: Operational transconductance amplifiers (OTAs) are widely used in the design of electronically tunable circuits. However, electronic tunability ranges of the OTA based filters are restricted by the limited bandwidth of the transconductance gain of the OTA. Furthermore, stability conditions and the linearity of the OTA which depends on the control current restrict the tunability. In this paper, some trade-offs in the electronically tunable filters are investigated. In addition, the tunability ranges of some first and second order OTA-C and OTA-RC filters are comparatively examined. Moreover, an OTA-C all-pass filter circuit is presented. SPICE simulations are performed and stability analyses are given for both of the OTA-C and OTA-RC filters. Operation of the presented all-pass filter is verified experimentally.

Pub.: 05 Feb '09, Pinned: 26 Aug '17

Performance comparison of high-order IFLF and LF linear phase lowpass OTA-C filters with and without gain boost

Abstract: Design and performance comparison of high-order operational transconductance amplifier and capacitor (OTA-C) filters using leapfrog (LF) and inverse-follow-the-leader-feedback (IFLF) structures are investigated. The filters are designed for a 125 MHz seventh-order equiripple group delay lowpass characteristic with and without gain boost and simulated in 0.25 μm 2-V CMOS. A fully differential highly linear OTA with cross-coupled input pairs and regulated cascode output is used for the simulation. Simulated results show that while the IFLF OTA-C filter can achieve a higher gain boost, the LF OTA-C filter has better other performances.

Pub.: 15 Nov '09, Pinned: 26 Aug '17

Realization of Tunable Pole-Q Current-Mode OTA-C Universal Filter

Abstract: A realization of a current-mode operational transconductance amplifier-capacitor (OTA-C) universal filter with tunable pole-Q is proposed. A biquadratic band-reject function is used as the initial synthesis function based on three integrator blocks. Consequently, the proposed filter uses a total of three multiple-output OTAs and three grounded capacitors. Five types of transfer functions, namely, low-pass, high-pass, band-pass, band-reject, and all-pass responses, can be obtained without changing the circuit topology. The pole-Q (Q0) and the pole-frequency (ω0) parameters are independently tuned. The Q0 and ω0 parameters are electronically tuned by adjusting the transconductance gains of the OTAs. Furthermore, Q0 can be tuned by varying the capacitor manually without affecting ω0. SPICE simulation results of the proposed filter are presented.

Pub.: 27 Apr '10, Pinned: 26 Aug '17

COMPLIMENTARY SINGLE-ENDED-INPUT OTA-C UNIVERSAL FILTER STRUCTURES

Abstract: A complimentary single-ended-input OTA-C universal filter structures in terms of integrated circuits is provided. The integrated circuit comprises a plurality of amplifiers and a plurality of capacitors. In some capacitors, one electrode is electrically connected to the positive input of its corresponding amplifier, and the other electrode can be electrically connected to an electrical source. In addition, the negative input of one amplifier is electrically connected to the negative input of another amplifier. Besides, there are a head amplifier and a tail amplifier. The output of the head amplifier is electrically connected to the negative input of the head amplifier, and the positive input of the tail amplifier can be electrically connected to an electrical source.

Pub.: 29 Dec '11, Pinned: 26 Aug '17

A frequency-translation technique for low-noise ultra-low-cutoff lowpass filtering

Abstract: Presented is a frequency-translation technique for compact realization of a low-noise lowpass filter (LPF) for biopotential acquisition systems. It is by chopper-stabilizing a bandpass filter (BPF) to obtain an ultra-low-cutoff lowpass response. This technique not only removes the BPF’s flicker noise and dc-offset, but also adds clock-based gain-bandwidth tunability and saves chip area because of highly relaxed time constants. A 1.4 to 15-Hz 2nd-order OTA-C ladder LPF designed in a 90-nm CMOS process verifies the merits of the technique with respect to the prior art.

Pub.: 04 Mar '12, Pinned: 26 Aug '17

Low-Noise Low-Pass Filter for ECG Portable Detection Systems with Digitally Programmable Range

Abstract: This paper presents the design of an operational transconductance amplifier-C (OTA-C) low-pass filter for a portable Electrocardiogram (ECG) detection system. A fifth-order Butterworth filter using ladder topology is utilized to reduce the effect of component tolerance and to provide a maximally flat response. The proposed filter is based on a novel class AB digitally programmable fully differential OTA circuit. Based on this, PSPICE simulation results for the filter using 0.25-μm technology and operating under ±0.8 V voltage supply are also given. The filter provides a third harmonic distortion (HD3) of 53.5 dB for 100 mV p-p @50 Hz sinusoidal input, input referred noise spectral density of , total power consumption of 30 μW, and a bandwidth of 243 Hz. These results demonstrate the ability of the filter to be used for ECG signal filtering that is located within 150 Hz.

Pub.: 13 Feb '13, Pinned: 26 Aug '17

Complimentary single-ended-input OTA-C universal filter structures

Pub.: 11 Jun '13, Pinned: 26 Aug '17

OTA-based current-mode filter and oscillator

Abstract: Techniques are generally described herein related to filters including first operational transconductance amplifier (first OTA) and a second operational transconductance amplifier (second OTA). In some examples described herein, the first OTA and second OTA have substantially the same transconductance. The first and second OTAs can be configured to realize filters such as first-order all-pass filters, second-order all-pass filters, higher-order all-pass filters, and quadrature oscillators.

Pub.: 25 Feb '14, Pinned: 26 Aug '17

Six Order Cascaded Power Line Notch Filter for ECG Detection Systems with Noise Shaping

Abstract: This paper presents the design of an operational transconductance amplifier-C (OTA-C) notch filter for a portable Electrocardiogram (ECG) detection system. A six order cascaded filter is utilized to reduce the effect of the power line interference at (50/60 Hz). The proposed filter is based on a programmable balanced OTA circuit. Based on this, PSPICE post layout simulation results for the extracted filter using 0.25 $\upmu $m technology and operating under $\pm $0.8 V voltage supply are also given. The six order notch filter provides a notch depth of 65 dB (43 dB for 4th order), input referred noise spectral density with noise shaping of 9 $\upmu $Vrms/$\surd $Hz at the pass band frequencies and 9 mVrms/$\surd $Hz at the notch (zero) frequency which provide noise shaping for the ECG signal. These results demonstrate the ability of the filter to be used for ECG signal filtering which is located within 150 Hz.

Pub.: 14 Mar '14, Pinned: 26 Aug '17

Apparatus and method for tuning a GM-C filter

Abstract: An apparatus to control a tuneable Gm-C filter, including and a filter that can be reconfigured as a free running oscillator by toggling the feedback sign of an output amplifier (304), a digital controller (42), sensitive to the output of the filter in the calibration configuration, and a DAC (44) to provide an analogue control signal (48) to the gm inputs of the transconductance amplifiers (310, 320) composing the filter.

Pub.: 19 Aug '14, Pinned: 26 Aug '17

Design for testability of high‐order OTA‐C filters

Abstract: A study of oscillation‐based test for high‐order Operational Transconductance Amplifier‐C (OTA‐C) filters is presented. The method is based on partition of a high‐order filter into second‐order filter functions. The opening Q‐loop and adding positive feedback techniques are developed to convert the second‐order filter section into a quadrature oscillator. These techniques are based on an open‐loop configuration and an additional positive feedback configuration. Implementation of the two testability design methods for nth‐order cascade, IFLF and leapfrog (LF) filters is presented, and the area overhead of the modified circuits is also discussed. The performances of the presented techniques are investigated. Fourth‐order cascade, inverse follow‐the‐leader feedback (IFLF) and LF OTA‐C filters were designed and simulated for analysis of fault coverage using the adding positive feedback method based on an analogue multiplexer. Simulation results show that the oscillation‐based test method using positive feedback provides high fault coverage of around 97%, 96% and 95% for the cascade, IFLF and LF OTA‐C filters, respectively. Copyright © 2016 John Wiley & Sons, Ltd.

Pub.: 12 Feb '16, Pinned: 26 Aug '17

Reconfigurable intergrator/differentiator circuit based on current follower

Abstract: A reconfigurable integrator/Differentiator circuit includes: a first input terminal; a first output terminal; a first current follower amplifier having a second input terminal, a second inverting output terminal, and a third non-inverting output terminal, wherein the second inverting output terminal provides feed back to the first input terminal and the third non-inverting output terminal is directly connected to the first output terminal; a second current follower amplifier having a third input terminal, a fourth inverting output terminal, and a fifth non-inverting output terminal, wherein the fourth inverting output terminal provides feed back to the first input terminal and the fifth non-inverting output terminal is directly connected to the first output terminal; a single resistor being connected between the first input terminal and the second input terminal, and a single capacitor being connected between the first input terminal and the third input terminal.

Pub.: 05 Apr '16, Pinned: 26 Aug '17

Ultra-low frequency bio-medical active-RC lowpass filters

Abstract: Active-RC low-pass filters based on R-0.5R ladders are implemented to provide high linear and low power design solutions for integrated biomedical applications. Among various R-αR ladders family, R-0.5R ladders provide the best low frequency selectivity characteristics. The filters exhibit ultra-low pole frequencies and occupy relatively compact silicon areas by using the R-0.5R ladders.

Pub.: 07 Feb '17, Pinned: 26 Aug '17

Field programmable analog array

Abstract: In an embodiment, a field programmable analog array (FPAA) comprises state variable filter engines arranged in parallel, each state variable filter engine comprising at least one variable attenuator and at least one variable integrator configured to operate on a wideband analog signal; and a summer configured to add outputs from the state variable filter engines.

Pub.: 03 Mar '15, Pinned: 26 Aug '17

Gradient and passive circuit structure in a class of non-linear dynamics on a graph

Abstract: Publication date: October 2016 Source:Systems & Control Letters, Volume 96 Author(s): Herbert Mangesius, Jean-Charles Delvenne, Sanjoy K. Mitter We consider a class of non-linear dynamics on a graph that contains and generalizes various models from network systems and control and study convergence to uniform agreement states using gradient methods. In particular, under the assumption of detailed balance, we provide a method to formulate the governing ODE system in gradient descent form of sum-separable energy functions, which thus represent a class of Lyapunov functions; this class coincides with Csiszár’s information divergences. Our approach bases on a transformation of the original problem to a mass-preserving transport problem and it reflects a little-noticed general structure result for passive network synthesis obtained by B.D.O. Anderson and P.J. Moylan in 1975. The proposed gradient formulation extends known gradient results in dynamical systems obtained recently by M. Erbar and J. Maas in the context of porous medium equations. Furthermore, we exhibit a novel relationship between inhomogeneous Markov chains and passive non-linear circuits through gradient systems, and show that passivity of resistor elements is equivalent to strict convexity of sum-separable stored energy. Eventually, we discuss our results at the intersection of Markov chains and network systems under sinusoidal coupling.

Pub.: 27 Jul '16, Pinned: 26 Aug '17

Analogue and Mixed-Signal Systems Topologies Exploration Using Symbolic Methods

Abstract: This paper describes the use of symbolic methods applied to the automatic exploration and characterisation of analogue and mixed-signal systems topologies and architectures. The developed methodology acquires the desired system requirements at the algorithm-level, using an HDL description, and employs, both, a modified signal flow graph approach and a pattern recognition techniques for synthesis purposes, leading to a complete characterisation of the sub-blocks from the automatically generated architecture. Thus, by allowing the synthesis process to move into higher levels of abstraction, the proposed methodology provides a computer-based framework for the systematic and uniform treatment of various types of data conversion systems, including the search for new conversion algorithms and/or new implementing architectures. The discussion will be centered on a developed methodology for high-level synthesis of data conversion systems both linear and non-linear, and how the presented methodology might be expanded to synthesize other analogue structures.

Pub.: 01 May '02, Pinned: 26 Aug '17

Efficient Decomposition Techniques for Symbolic Analysis of Large-Scale Analog Circuits by State Variable Method

Abstract: New tearing techniques for the systematic formulation of the state equations in symbolic normal-form for linear and nonlinear time-invariant large-scale analog circuits are developed. Some examples are given to illustrate the decomposition procedure and the assignment of the connection sources. The partial symbolic state equations of the opamp μA 741 are obtained using the tearing approach, while these equations cannot be written working on the whole circuit.

Pub.: 01 Sep '04, Pinned: 26 Aug '17

Systematic Synthesis of Active-RC Circuit Building-Blocks

Abstract: In this paper, we show how some basic building blocks for active-RC circuit design, such as amplifiers, impedance converters and simulated inductance circuits, may be synthesised in a systematic way by expansion of their port admittance matrices. The circuit topology emerges from the synthesis procedure, allowing all possible implementations to be identified and explored. Nullors representing ideal op-amps and transistors are represented within the nodal admittance matrix of a synthesised circuit by linked infinity parameters. In nodal admittance matrices describing ideal circuits synthesised, the replacement of linked infinity parameters by finite parameters provides a seamless transition to non-ideal analysis and practical circuit design.

Pub.: 01 Jun '05, Pinned: 26 Aug '17

Analog Circuit Synthesis Using Linear and Nonlinear Current Amplifiers

Abstract: Various design techniques are presented for obtaining current-mode filters suitable for operation at high frequencies. For this purpose CMOS and or bipolar current amplifiers are used as active building blocks. The derived circuits simulate LC passive prototype filters. Second order resonators can also be obtained by following the same techniques. The presented circuits are modular in structure, thus, their electronic and layout design is very easy. Low-voltage, low-power design is also feasible. Simulation examples for all-pole filters and filters with transmission zeros are given.

Pub.: 01 Mar '06, Pinned: 26 Aug '17

Aladin: A Layout Synthesys Tool for Analog Integrated Circuits

Abstract: This paper presents a layout synthesis tool called ALADIN for analog integrated circuits. It is developed especially for analog circuit designers who can bring their special knowledge and experience into the synthesis process to create high quality layouts. The layout generation is based on relatively complex sub-circuits rather than non-optimal single devices. A flexible module generator environment is developed for designers to write and maintain technology and application independent module generators of sub-circuits. Based on the thorough study of simulated annealing and genetic algorithm applications in the analog module placement, a genetic placement approach with simulated annealing and a very fast simulated re-annealing placement approach have been developed. A two-stage placement technique is proposed. Analog module routing consists of two phases including global routing and detailed routing. The minimum-Steiner-tree based global routing can be integrated into the placement procedure to improve the routability of placement solutions. The compaction based constructive detailed routing finally realizes the layout of the whole circuit. This tool is integrated into commercial software with convenient interfaces provided. The benefit of ALADIN providing layouts comparable to expert manual ones is demonstrated with several circuits showing its competition compared to other existing tools.

Pub.: 01 Mar '06, Pinned: 26 Aug '17