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CURATOR
A pinboard by
Vinayaka Jyothi

PhD Student, NYU Tandon School of Engineering

PINBOARD SUMMARY

Tag and Track FPGAs to identify any type of counterfeiting

Advanced semiconductor technology nodes, shrinking gate sizes, and economic incentives have created a horizontal business model in the IC semiconductor industry; wherein the ICs are designed by one company, while fabricated in an offshore foundry by another company. Field Programmable Gate Arrays (FPGA) are no exception. This trend of separating design from fabrication leads to potential vulnerabilities in the IC supply chain. FPGAs can be overproduced by an offshore foundry, reverse engineered and cloned by an attacker, old and recycled FPGAs can be reinserted into the supply chain by a malicious distributor/vendor. These counterfeit FPGAs can also have Hardware Trojans that can leak information or allow a remote attacker to perform malicious operations. FPGA-Mark methodology creates a unique fingerprint called 'Mark,' which can be used by the vendor and the end-user to verify the FPGAs for manufacturer authenticity and detect counterfeit products. This way, FPGA-Mark incorporates 'Trust' into FPGA Supply Chain.

6 ITEMS PINNED

Towards the implementation of Multi-band Multi-standard Software-Defined Radio using Dynamic Partial Reconfiguration

Abstract: The vast evolution of fixed and mobile standards urges upgrading the hardware to be compatible with them. An efficient approach to reduce the required cost and effort is hardware reusability, which in turn can be achieved by a dynamically reconfigurable field programmable gate array (FPGA). This flexible hardware time multiplexing allows more logic to fit within the same area, which means fitting bigger designs into smaller less expensive devices, with more optimization of power consumption. This work shows the advantages of using the dynamic partial reconfiguration (DPR) technique, on a fine-grained block level, in implementing a baseband physical layer processing module for software-defined radio (SDR) chain that supports 3G, long-term evolution (LTE), and WIFI standards. The benefits increase when the reconfiguration is not only dynamic but also takes place in run-time without the need to switch off the system. A comparison is held on Xilinx Virtex 5 design kit XUPV5-LX110T between the implementation of the baseband processing module with and without using the DPR technique in the 3G, long-term evolution, and WIFI standards. The comparison addresses the area, power, memory, and time overhead. Experimental results reveal that the DPR technique improves the area and the power consumption with an acceptable increase in memory and latency. Xilinx ISE 14.7 is used for modules implementation, Xilinx PlanAhead is used in floorplanning for the different designs and applying the DPR technique, and Xilinx Power Analyzer is used to measure the power consumption.

Pub.: 08 Jun '17, Pinned: 29 Jun '17

A New Method for Neural Spike Alignment: The Centroid Filter.

Abstract: Recordings made directly from the nervous system are a key tool in experimental electrophysiology and the development of bioelectronic medicines. Analysis of these recordings involves the identification of signals from individual neurons, a process known as spike sorting. A critical and limiting feature of spike sorting is the need to align individual spikes in time. However, electrophysiological recordings are made in extremely noisy environments that seriously limit the performance of the spike-alignment process. We present a new centroid-based method and demonstrate its effectiveness using deterministic models of nerve signals. We show that spike alignment in the presence of noise is possible with a 30 dB reduction in minimum SNR compared to conventional methods. We present a mathematical analysis of the centroid method, characterising its fundamental operation and performance. Further, we show that the centroid method lends itself particularly well to hardware realisation and we present results from a low-power implementation that operates on an FPGA, consuming 10 times less power than conventional techniques - an important property for implanted devices. Our centroid method enables the accurate alignment of spikes in sub-0 dB SNR recordings and has the potential to enable the analysis of spikes in a wider range of environments than has been previously possible. Our method thus has the potential to influence significantly the design of electrophysiological recording systems in the future.

Pub.: 24 Jun '17, Pinned: 29 Jun '17