PhD Student, NYU Tandon School of Engineering
Tag and Track FPGAs to identify any type of counterfeiting
Advanced semiconductor technology nodes, shrinking gate sizes, and economic incentives have created a horizontal business model in the IC semiconductor industry; wherein the ICs are designed by one company, while fabricated in an offshore foundry by another company. Field Programmable Gate Arrays (FPGA) are no exception. This trend of separating design from fabrication leads to potential vulnerabilities in the IC supply chain. FPGAs can be overproduced by an offshore foundry, reverse engineered and cloned by an attacker, old and recycled FPGAs can be reinserted into the supply chain by a malicious distributor/vendor. These counterfeit FPGAs can also have Hardware Trojans that can leak information or allow a remote attacker to perform malicious operations. FPGA-Mark methodology creates a unique fingerprint called 'Mark,' which can be used by the vendor and the end-user to verify the FPGAs for manufacturer authenticity and detect counterfeit products. This way, FPGA-Mark incorporates 'Trust' into FPGA Supply Chain.
Abstract: Fast environmental variations due to climate change can cause mass decline or even extinctions of species, having a dramatic impact on the future of biodiversity. During the last decade, different approaches have been proposed to track and monitor endangered species, generally based on costly semi-automatic systems that require human supervision adding limitations in coverage and time. However, the recent emergence of Wireless Acoustic Sensor Networks (WASN) has allowed non-intrusive remote monitoring of endangered species in real time through the automatic identification of the sound they emit. In this work, an FPGA-based WASN centralized architecture is proposed and validated on a simulated operation environment. The feasibility of the architecture is evaluated in a case study designed to detect the threatened Botaurus stellaris among other 19 cohabiting birds species in The Parc Natural dels Aiguamolls de l'Empord.
Pub.: 09 Jun '17, Pinned: 29 Jun '17
Abstract: State-of-the-art technology for pulse counter electronics offers an important range of commercial devices, but such systems are usually expensive due to the complex logic used for this task. The use of counting electronics in conjunction with photon counters can be used, for example, to perform experimental tests in Quantum Optics and Quantum Information Science. Here, we present the development and implementation of a low cost module for multiphoton coincidence statistics with detection windows of a few nanoseconds. The module consists of an array of logic gates, with a frequency operation of 250 MHz that corrects and amplifies the detectors signal. The device characterisation was done by means of detection of Transistor-Transistor Logic (TTL) signals retrieved from a signal generator, and implemented in an optical setup. The detected output signals (TTL pulses) were analysed and stored in a computer by means of a Field Programmable Gate Array (FPGA). Our module incorporates fundamental electronics that is currently used in the first experimental proof-of-principle tests in quantum information and molecular spectroscopy at CIBioFi.
Pub.: 15 Jun '17, Pinned: 29 Jun '17
Abstract: Cameras are the defacto sensor. The growing demand for real-time and low-power computer vision, coupled with trends towards high-efficiency heterogeneous systems, has given rise to a wide range of image processing acceleration techniques at the camera node and in the cloud. In this paper, we characterize two novel camera systems that employ acceleration techniques to push the extremes of energy and performance scaling, and explore the computation-communication tradeoffs in their designs. The first case study is a camera system designed to detect and authenticate individual faces, running solely on energy harvested from RFID readers. We design a multi-accelerator SoC design operating in the sub-mW range, and evaluate it with real-world workloads to show performance and energy efficiency improvements over a general purpose microprocessor. The second camera system is a 16-camera rig processing over 32 Gb/s of data to produce real-time 3D-360 degree virtual reality video. We design a multi-FPGA processing pipeline that outperforms CPU and GPU configurations by up to 10$\times$ in the computation time, producing panoramic stereo video directly from the camera rig at 30 frames per second. We find that an early data reduction step, either before complex processing or offloading, is the most critical optimization for in-camera systems.
Pub.: 12 Jun '17, Pinned: 29 Jun '17
Abstract: The vast evolution of fixed and mobile standards urges upgrading the hardware to be compatible with them. An efficient approach to reduce the required cost and effort is hardware reusability, which in turn can be achieved by a dynamically reconfigurable field programmable gate array (FPGA). This flexible hardware time multiplexing allows more logic to fit within the same area, which means fitting bigger designs into smaller less expensive devices, with more optimization of power consumption. This work shows the advantages of using the dynamic partial reconfiguration (DPR) technique, on a fine-grained block level, in implementing a baseband physical layer processing module for software-defined radio (SDR) chain that supports 3G, long-term evolution (LTE), and WIFI standards. The benefits increase when the reconfiguration is not only dynamic but also takes place in run-time without the need to switch off the system. A comparison is held on Xilinx Virtex 5 design kit XUPV5-LX110T between the implementation of the baseband processing module with and without using the DPR technique in the 3G, long-term evolution, and WIFI standards. The comparison addresses the area, power, memory, and time overhead. Experimental results reveal that the DPR technique improves the area and the power consumption with an acceptable increase in memory and latency. Xilinx ISE 14.7 is used for modules implementation, Xilinx PlanAhead is used in floorplanning for the different designs and applying the DPR technique, and Xilinx Power Analyzer is used to measure the power consumption.
Pub.: 08 Jun '17, Pinned: 29 Jun '17
Abstract: Rapid and low power computation of optical flow (OF) is potentially useful in robotics. The dynamic vision sensor (DVS) event camera produces quick and sparse output, and has high dynamic range, but conventional OF algorithms are frame-based and cannot be directly used with event-based cameras. Previous DVS OF methods do not work well with dense textured input and are designed for implementation in logic circuits. This paper proposes a new block-matching based DVS OF algorithm which is inspired by motion estimation methods used for MPEG video compression. The algorithm was implemented both in software and on FPGA. For each event, it computes the motion direction as one of 9 directions. The speed of the motion is set by the sample interval. Results show that the Average Angular Error can be improved by 30\% compared with previous methods. The OF can be calculated on FPGA with 50\,MHz clock in 0.2\,us per event (11 clock cycles), 20 times faster than a Java software implementation running on a desktop PC. Sample data is shown that the method works on scenes dominated by edges, sparse features, and dense texture.
Pub.: 16 Jun '17, Pinned: 29 Jun '17
Abstract: Recordings made directly from the nervous system are a key tool in experimental electrophysiology and the development of bioelectronic medicines. Analysis of these recordings involves the identification of signals from individual neurons, a process known as spike sorting. A critical and limiting feature of spike sorting is the need to align individual spikes in time. However, electrophysiological recordings are made in extremely noisy environments that seriously limit the performance of the spike-alignment process. We present a new centroid-based method and demonstrate its effectiveness using deterministic models of nerve signals. We show that spike alignment in the presence of noise is possible with a 30 dB reduction in minimum SNR compared to conventional methods. We present a mathematical analysis of the centroid method, characterising its fundamental operation and performance. Further, we show that the centroid method lends itself particularly well to hardware realisation and we present results from a low-power implementation that operates on an FPGA, consuming 10 times less power than conventional techniques - an important property for implanted devices. Our centroid method enables the accurate alignment of spikes in sub-0 dB SNR recordings and has the potential to enable the analysis of spikes in a wider range of environments than has been previously possible. Our method thus has the potential to influence significantly the design of electrophysiological recording systems in the future.
Pub.: 24 Jun '17, Pinned: 29 Jun '17