PhD Scholar, Indian Institute of Technology Kharagpur
My current research topic focuses on lightweight, efficient and secure design of ECC on FPGAs
Light-weight hardware devices embedded in RFID tags, wireless sensor nodes are just a glimpse of the uprising Internet-of-Things. This recent boom of Internet-of-Things enhances the importance of implementation of asymmetric key cryptography in embedded devices. The front runners of public key cryptography are RSA crypto-system and Elliptic curve cryptography, out of which ECC suits more for the purpose of embedded device security for its wonderful property of providing more security per key bit than its counterpart RSA. For example, 160 bit ECC is comparable to 1024 bit RSA security. Due to the reduced key size, public key protocols like Diffie-Hellman key exchange or digital signature algorithm based on ECC will be more compact, lightweight and less resource hungry compared to RSA based algorithms. In this research, our objective is to develop different implementations of ECC on FPGAs, targeting different applications. We have developed a lightweight version of ECC, focussing on lightweight applications like IoT. Additionally, we have developed a high-speed version of ECC targeting applications like self-driving automatic cars where high-speed real time processing of data are required. Moreover, these implementations can be subjected to attacks like power and electromagnetic radiation based side channel attacks. In this scenario, the adversary will try to break the underlying ECC by observing physical information like timing performance and power consumption of the device. The developed implementations also can be integrated easily with side channel countermeasures to prevent such attacks. More specifically, the published paper in the conference "PROOFS" talks about extremely lightweight side channel countermeasure which prevents a specific side channel attack, known as horizontal collision correlation analysis. The proposed countermeasure can be easily integrated during the implementation of FPGA and has zero overhead in some scenarios, making it extremely efficient.
Abstract: Cryptographic algorithms are computationally costly and the challenge is more if we need to execute them in resource constrained embedded systems. Field Programmable Gate Arrays (FPGAs) having programmable logic de- vices and processing cores, have proven to be highly feasible implementation platforms for embedded systems providing lesser design time and reconfig- urability. Design parameters like throughput, resource utilization and power requirements are the key issues. The popular Elliptic Curve Cryptography (ECC), which is superior over other public-key crypto-systems like RSA in many ways, such as providing greater security for a smaller key size, is cho- sen in this work and the possibilities of its implementation in FPGA based embedded systems for both single and dual processor core architectures in- volving task parallelization have been explored. This exploration, which is first of its kind considering the other existing works, is a needed activity for evaluating the best possible architectural environment for ECC implementa- tion on FPGA (Virtex4 XC4VFX12, FF668, -10) based embedded platform.
Pub.: 14 Jan '14, Pinned: 31 Aug '17
Abstract: This article proposes a novel architecture to perform modular multiplication in the Residue Number System (RNS) by using sum of residues. The highly parallel architecture is implemented using VHDL and verified by extensive simulations in ModelSim SE. The pipelined and non-pipelined versions of the design are implemented on ASIC and FPGA platforms to allow a broad comparison. The proposed architecture requires only one iteration to complete modular multiplication and achieves 12–90 % less delay as compared to the existing RNS and binary modular multipliers. The complexity of the proposed design is also less than the existing state-of-the-art RNS-based modular multipliers. The high scalability and flexibility of the proposed architecture allows it to be used for a wide range of high-speed applications.
Pub.: 19 May '16, Pinned: 31 Aug '17
Abstract: Elliptic curve cryptography (ECC) is a branch of Public-Key cryptography that is widely accepted for secure data exchange in many resource-limited devices. This paper presents a novel hardware cryptographic processor for ECC over general prime field GF(p). It is optimized on circuit level by introducing new parallel modular multiplication algorithm with its efficient hardware architecture, which offers significant improvement over the previously used techniques. Subsequently, on the system level, it is optimized by exploiting available high degree of parallelism using projective coordinates by incorporating four parallel multiplier units. The proposed hardware is implemented on Xilinx Virtex-4 and Virtex-6 field programmable gate arrays. A 256-bit scalar multiplication is completed in 1.43 ms and 2.96 ms in a cycle count of 207 1K on Virtex-6 and Virtex-4 field programmable gate array paltforms, respectively. The Virtex-6 implementation attains a maximum frequency of 144 MHz, occupies 32 4K look-up-tables, whereas on Virtex-4 it is about 70 MHz with 35 7K slices. The results show that the proposed design offers a significant improvement in computation time with a significant reduction in cycle count as compared with the other reported designs. Therefore, it is a good choice to be used in many ECC-based schemes. Copyright © 2016 John Wiley & Sons, Ltd.
Pub.: 07 Dec '16, Pinned: 31 Aug '17
Abstract: Publication date: Available online 10 December 2016 Source:Microprocessors and Microsystems Author(s): Khalid Javeed, Xiaojun Wang, Mike Scott Secure information exchange in resource constrained devices can be accomplished efficiently through elliptic curve cryptography (ECC). Due to the high computational complexity of ECC arithmetic, a high performance dedicated hardware architecture is essential to provide sufficient performance in a computation of elliptic curve scalar multiplication. This paper presents a high performance hardware support for elliptic curve cryptography over a prime field GF(p). It exploited a best available possible parallelism of elliptic curve points in projective representation. The proposed hardware for ECC is implemented on Xilinx Virtex-4, Virtex-5 and Virtex-6 FPGAs. A 256-bit scalar multiplication is completed in 2.01 ms, 2.62 ms and 3.91 ms on Virtex-6, Virtex-5 and Virtex-4 FPGA paltforms, respectively. The results show that the proposed design is 1.96 times faster with insignificant increase in area consumption as compared to the other reported designs. Therefore, it is a good choice to be used in many ECC based schemes.
Pub.: 10 Dec '16, Pinned: 31 Aug '17