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Test structure to monitor the effects of polysilicon pre-doping

Imported: 23 Feb '17 | Published: 22 Oct '02

John J. Bush, Mark I. Gardner, David E. Brown

USPTO - Utility Patents

Abstract

Various embodiments of a test circuit and methods of fabricating and using the same are provided. In one aspect, a test circuit includes a semiconductor substrate and a mask thereon that has an opening to enable impurity doping of selected portions of the test circuit. A plurality of circuit devices are provided on the substrate that have respective active regions positioned at staggered known distances from the mask opening. Each of the plurality of circuit devices has a gate electrode that extends to the opening and has a first impurity region of a first conductivity type and a second impurity region of a second and opposite conductivity type. Where the predicted on-state output current of a given circuit device exceeds an actual output current of the given circuit device, there is indication of an overlap between the first and second impurity regions of the gate electrode of the given device.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other advantages of the invention will become apparent upon reading the following detailed description and upon reference to the drawings in which:

FIG. 1 is an overhead view of an exemplary conventional integrated circuit incorporating n-channel poly pre-doping;

FIG. 2 is a plan view of the integrated circuit of FIG. 1 following fabrication thereon of a photomask with an implant window;

FIG. 3 is an overhead view of an exemplary embodiment of a test circuit suitable for determining the critical spacing between circuit devices and the edge of a pre-doping mask opening in accordance with the present invention;

FIG. 4 is an overhead view like FIG. 3 depicting removal of the pre-doping mask to expose the previously covered portions of the test circuit in accordance with the present invention;

FIG. 5 is an overhead view like FIG. 4 depicting an anneal to activate the source/drain regions of the circuit devices of the test circuit in accordance with the present invention; and

FIG. 6 is an overhead view of an alternate exemplary embodiment of a test circuit suitable for determining the critical spacing between circuit devices and the edge of a pre-doping mask opening in accordance with the present invention.

Claims

1. A test circuit, comprising:

2. The test circuit of claim 1, wherein the predicted on-state output current comprises the predicted drain saturation current.

3. The test circuit of claim 1, wherein the lesser of the staggered known distances in which there is no overlap between the second impurity region and the active region of a given device defines a minimum desirable spacing between the first edge of the mask opening and an active circuit device.

4. The test circuit of claim 1, wherein the first conductivity type comprises p-type and the second conductivity type comprises n-type.

5. The test circuit of claim 1, wherein the first source/drain regions of each of the plurality of circuit devices being commonly connected to a conductor.

6. A test circuit, comprising:

7. The test circuit of claim 6, wherein the predicted on-state output current comprises the predicted drain saturation current.

8. The test circuit of claim 6, wherein the lesser of the known distances in which there is no overlap between the second impurity region and the active region of a given field effect transistor defines a minimum desirable spacing between the first edge of the mask opening and an active field effect transistor.

9. The test circuit of claim 6, wherein the first conductivity type comprises p-type and the second conductivity type comprises n-type.

10. The test circuit of claim 6, wherein the first source/drain regions of the plurality of field effect transistors are commonly connected to a conductor.

11. The test circuit of claim 6, wherein the second source/drain regions of two of the plurality of field effect transistors being commonly connected to a conductor, the two field effect transistors having a width measured from their second edges in a direction away from the first edge of the mask opening, the known distance between one of the two field effect transistors and the first edge of the mask opening differing from the known distance between the other of the two field effect transistors and the first edge of the mask opening by at least the width.

12. A test circuit, comprising:

13. The test circuit of claim 12, wherein the predicted on-state output current comprises the predicted drain saturation current.

14. The test circuit of claim 13, wherein the lesser of the staggered known distances in which there is no overlap between the second impurity region and the active region of a given device defies a minimum desirable spacing between the first edge of the mask opening and an active circuit device.

15. The test circuit of claim 13, wherein the first conductivity type comprises p-type and the second conductivity type comprises n-type.

16. The test circuit of claim 13, wherein the first source/drain regions of each of the plurality of circuit devices being commonly connected to a conductor.