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Structure for reducing contact aspect ratios

Imported: 23 Feb '17 | Published: 22 Oct '02

Scott J. Deboer, Vishnu K. Agarwal

USPTO - Utility Patents

Abstract

An intermediate metal plug is used to raise the platform to which contact is to be made. In the illustrated process, a partial bit line plug is formed adjacent a stacked capacitor, and an interlevel dielectric formed over the capacitor. The bit line contact is completed by extending a via from the bit line, formed above the interlevel dielectric, down to the level of the intermediate plug, and the via is filled with metal. The height of the via to be filled is thus reduced by the height of the intermediate plug. In one embodiment, the intermediate plug is slightly shorter than an adjacent container-shaped capacitor. In another embodiment, the intermediate plug is about as high as an adjacent stud capacitor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

These and other aspects of the invention will be readily apparent from the attached detailed description, claims and drawings, wherein like numerals will be used to refer to like parts, and in which:

FIG. 1 is a partial, schematic, sectional view of a partially fabricated integrated circuit, constructed in accordance with a preferred embodiment of the present invention, having a plurality of transistors formed therein and a first interlevel dielectric covering the transistors;

FIG. 2 shows the integrated circuit of FIG. 1 after a plurality of conductive plugs are formed through the first interlevel dielectric to contact the transistor active areas;

FIG. 3A shows the integrated circuit of FIG. 2 after a second interlevel dielectric layer is formed and conductive plugs formed therethrough to electrically contact the underlying plugs;

FIG. 3B shows the integrated circuit of FIG. 3A after a third interlevel dielectric layer has been deposited and etched to expose certain of the underlying conductive plugs, while shielding other conductive plugs;

FIG. 4 illustrates the integrated circuit of FIG. 3B after the exposed conductive plugs have been removed, and a conformal conductive layer deposited over the wafer;

FIG. 5 illustrates the integrated circuit of FIG. 4 after the conformal conductive layer has been patterned to define capacitor bottom electrodes, and capacitor dielectric and top electrode layers deposited thereover;

FIG. 6 illustrates the integrated circuit of FIG. 5 after a window has been formed through the top electrode;

FIG. 7 illustrates the integrated circuit of FIG. 6 after a fourth interlevel dielectric has been deposited;

FIG. 8 shows the integrated circuit of FIG. 7 after formation of a bit line contact through the window;

FIG. 9 is a partial, schematic, sectional view of a partially fabricated integrated circuit, constructed in accordance with another embodiment of the invention, having a plurality of aligned conductive plugs formed through two interlevel dielectric layers that cover the transistors;

FIG. 10 shows the integrated circuit of FIG. 10 after the second interlevel dielectric has been substantially removed, except for sidewall spacers surrounding a partial bit line plug;

FIG. 11 shows the integrated circuit of FIG. 10 after formation of capacitor dielectric and top electrode layers;

FIG. 12 shows the integrated circuit of FIG. 11 after a window has been opened in the top electrode and capacitor dielectric over the partial bit line plug;

FIG. 13 shows the integrated circuit of FIG. 12 after a third interlevel dielectric has been deposited; and

FIG. 14 shows the integrated circuit of FIG. 13 after extension of the bit line plug and formation of a bit line.

Claims

1. An integrated circuit contact extending from a lower level to an upper level, the contact comprising:

2. The integrated circuit contact of claim 1, wherein the upper level comprises a metal wiring layer and the lower level comprises a semiconductor substrate.

3. The integrated circuit contact of claim 2, wherein the metal wiring layer comprises a bit line in a memory array.

4. The integrated circuit contact of claim 3, wherein the bit line extends over a plurality of cell capacitors in the memory array.

5. The integrated circuit contact of claim 4, wherein the first plug extends from the substrate to a bottom level of the cell capacitors.

6. The integrated circuit contact of claim 5, wherein the second plug extends from the first plug to a level below a top level of the cell capacitors.

7. The integrated circuit contact of claim 5, wherein the second plug extends from the first plug to approximately a top level of the cell capacitors.

8. The integrated circuit contact of claim 1, wherein the first plug comprises polysilicon, the second plug comprises metal, and the third plug comprises metal.

9. The integrated circuit contact of claim 8, wherein the second plug comprises elemental tungsten.

10. The integrated circuit contact of claim 8, wherein the second plug further comprises a conformal via liner.

11. The integrated circuit contact of claim 8, wherein the third plug comprises aluminium.

12. An integrated circuit contact extending from a lower level to an upper level, the contact comprising: