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Soft programming method for non-volatile memory cells

Imported: 23 Feb '17 | Published: 22 Oct '02

Guido de Sandre, Marco Pasotti, Pier Luigi Rolandi

USPTO - Utility Patents

Abstract

The optimized soft programming method is used in a memory consisting of a plurality of cells that are grouped into sectors. The cells that belong to a single sector have gate terminals connected to a plurality of word lines, and drain terminals connected to a plurality of local bit lines. The soft programming method consists of selecting at least one local bit line in the sector, and simultaneously selecting all the word lines in the same sector. A corresponding gate voltage is applied to all the word lines, whereas a constant drain voltage, with a pre-determined value is applied to the local bit line.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The characteristics and advantages of the method according to the invention will become apparent from the following description of an embodiment provided by way of indicative, non-limiting example, with reference to the attached drawings, in which:

FIG. 1 shows the development of an electrical value used in the erasing phase of a known non-volatile memory;

FIG. 2 shows a simplified electrical diagram of a non-volatile memory according to the invention;

and FIGS. 3

a and

3

b show the development of electrical values used in order to implement the method for soft programming of the memory in FIG. 2, according to the invention.

Claims

1. Soft programming method for a non-volatile memory comprising a plurality of cells which are grouped into a plurality of sectors, the cells belonging to a single sector having gate terminals connected to a plurality of word lines, which are connected to a global row decoder, and having drain terminals connected to a plurality of local bit lines, which are connected to a local column decoder,

wherein said method comprises:

2. Method according to claim 1, wherein said phase of applying a drain voltage consists of applying a positive potential with a pre-determined value.

3. Method according to claim 1, wherein said gate voltage is a ramp voltage.

4. Method according to claim 1, wherein said gate voltage is a rectangular pulse.

5. Method according to claim 1, wherein said gate voltage is a sequence of pulses.

6. Method according to claim 1, wherein said cells belonging to said single sector comprise source terminals connected to source lines, said source lines being connected to one another and to a common source line, and wherein said method comprises the phase of applying a reference potential to said common source line.

7. Method according to claim 1, wherein said cells belonging to said single sector comprise bulk regions connected to one another and to a common bulk line, and wherein said method comprises the phase of applying a negative potential with a pre-determined value to said common bulk line.

8. A method of programming a sector of a plurality of memory cells comprising:

9. Method according to claim 8 wherein the step of applying the third voltage level comprises:

10. Method according to claim 8 wherein the step of applying the third voltage level comprises:

11. Method according to claim 8 wherein the step of applying the third voltage level comprises:

12. A memory device comprising:

13. The memory device of claim 12, wherein said first selected voltage potential is a negative voltage between −0.5 and −1.5 volts.

14. The memory device of claim 12, wherein said second selected voltage potential is at ground.

15. The memory device of claim 12, wherein said fourth selected voltage potential is a between 4 and 5 Volts.

16. The memory device of claim 12, wherein said third selected voltage potential is between −1 Volt and 4 Volts.

17. The memory device according to claim 16, wherein said third selected voltage potential has a duration of 200-400 s.

18. The memory device according to claim 17, wherein said third selected voltage potential comprises a ramp voltage.

19. The memory device according to claim 17, wherein said third selected voltage potential comprises a rectangular pulse.

20. The memory device according to claim 17, wherein said third selected voltage potential comprises a series of shorter pulses.