Semiconductor memory having a memory cell array

A semiconductor memory such as, for example, a DRAM (Dynamic Random Access Memory) includes a memory cell array and an addressing periphery. A first memory cell having a first selection transistor and a first storage capacitor, and a second memory cell having a second selection transistor and a second storage capacitor are configured in the memory cell array. The first selection transistor is designed as an n-channel transistor and the second selection transistor is designed as a p-channel transistor. This makes it possible to realize a folded bit line concept for memory cells which are smaller than 8F

2.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a plan view of a configuration of memory cells including selection transistors and storage capacitors, with p- and n-channel transistors being formed;

FIG. 2 shows a sectional diagram along the section line Bn—Bn shown FIG. 1 with the memory cells constructed for stacked capacitors;

FIG. 3 shows a sectional diagram along the section line Bp—Bp shown in FIG. 1 with the memory cells constructed for stacked capacitors;

FIG. 4 shows a sectional diagram along the section line Bn—Bn shown FIG. 1, with the STI (Shallow Trench Isolation) not having been formed as far as the insulation layer of the SOI substrate (Silicon on Insulator);

FIG. 5 shows a sectional diagram along the section line Bp—Bp shown in FIG. 1, likewise with raised STI;

FIG. 6 shows a sectional diagram along the section plane A—A shown in FIG. 1;

FIG. 7 shows a sectional diagram along the section line Bn—Bn shown in FIG. 1 with trench capacitors;

FIG. 8 shows a sectional diagram along the section line Bp—Bp shown in FIG. 1 with trench capacitors;

FIG. 9 shows a sectional diagram along the section line Bn—Bn shown in FIG. 1 with trench capacitors and raised STI;

FIG. 10 shows a sectional diagram along the section line Bp—Bp shown in FIG. 1 with trench capacitors and raised STI;

FIG. 11 shows a sectional diagram along the section line A—A shown in FIG. 1 with trench capacitors;

FIG. 12 shows a plan view of a configuration of memory cells including selection transistors and storage capacitors, the selection transistors being designed as n-channel transistors and p-channel transistors;

FIG. 13 shows a plan view of an enlarged region from FIG.

12 and in which the course of the word lines has been enlarged;

FIG. 14 shows a sectional diagram along the section line Dn—Dn shown in FIG. 12 with trench capacitors;

FIG. 15 shows a sectional diagram along the section line Dp—Dp shown in FIG. 12 with trench capacitors; and

FIG. 16 shows a sectional diagram along the section line C—C shown in FIG.

12.

1. A semiconductor memory having a memory cell array, the memory cell array comprising:

2. The semiconductor memory according to claim 1, wherein at least one of said first storage capacitor and said second storage capacitor is formed as a trench capacitor.

3. The semiconductor memory according to claim 1, wherein at least one of said first storage capacitor and said second storage capacitor is formed as a stacked capacitor.

4. The semiconductor memory according to claim 1, wherein said first selection transistor is formed as a vertical transistor.

5. The semiconductor memory according to claim 1, wherein said second selection transistor is formed as a vertical transistor.

6. The semiconductor memory according to claim 4, comprising:

7. The semiconductor memory according to claim 1, wherein:

8. The semiconductor memory according to claim 7, comprising germanium provided as a dopant material.

9. The semiconductor memory according to claim 1, wherein:

10. The semiconductor memory according to claim 8, wherein said dopant is germanium.

11. The semiconductor memory according to claim 1, wherein said first selection transistor includes a gate material selected from the group consisting of titanium nitride, tungsten, and tantalum.

12. The semiconductor memory according to claim 1, wherein said second selection transistor includes a gate material selected from the group consisting of titanium nitride, tungsten, and tantalum.

13. The semiconductor memory according to claim 1, comprising:

14. The semiconductor memory according to claim 1, comprising: