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Semiconductor memory device having different distances between gate electrode layers

Imported: 23 Feb '17 | Published: 22 Oct '02

Takashi Kumagai, Masahiro Takeuchi, Satoru Kodaira, Takafumi Noda

USPTO - Utility Patents

Abstract

The invention provides SRAMs that can reduce memory cells in size and correct light proximity effect. Gate electrode layers in a first layer, drain-drain connection layers in a second layer, and drain-gate connection layers in a third layer define conduction layers of a flip-flop. A source contact layer of load transistors are located adjacent end sections of the gate electrode layers, and both of the end sections bend outwardly to avoid contact with the source contact layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view of first, second and third conduction layers in a part of a memory cell array in accordance with one embodiment of the present invention;

FIG. 2 is a plan view of a field in a part of the memory cell array in accordance with one embodiment of the present invention;

FIG. 3 is a plan view of a first conduction layer in a part of the memory cell array in accordance with one embodiment of the present invention;

FIG. 4 is a plan view of a plug

61 in a part of the memory cell array in accordance with one embodiment of the present invention;

FIG. 5 is a plan view of a second conduction layer in a part of the memory cell array in accordance with one embodiment of the present invention;

FIG. 6 is a plan view of a plug

73 in a part of the memory cell array in accordance with one embodiment of the present invention;

FIG. 7 is a plan view of a plug

75 in a part of the memory cell array in accordance with one embodiment of the present invention;

FIG. 8 is a plan view of a third conduction layer in a part of the memory cell array in accordance with one embodiment of the present invention;

FIG. 9 is a plan view of a plug

81 in a part of the memory cell array in accordance with one embodiment of the present invention;

FIG. 10 is a plan view of a fourth conduction layer in a part of the memory cell array in accordance with one embodiment of the present invention;

FIG. 11 is a plan view of the field, the first layer and the plug

61 in accordance with one embodiment of the present invention;

FIG. 12 is a plan view of the second layer and the plugs

73 and

75 in accordance with one embodiment of the present invention;

FIG. 13 is a plan view of the third layer and the plug

81 in accordance with one embodiment of the present invention;

FIG. 14 is a cross-sectional view taken along lines B

1-B

2 shown in a plan view in accordance with one embodiment of the present invention;

FIG. 15 is a cross-sectional view taken along lines C

1-C

2 shown in a plan view in accordance with one embodiment of the present invention;

FIG. 16 is an equivalent circuit of an SRAM in accordance with one embodiment of the present invention;

FIG. 17 is a plan view of mask patterns for gate electrode layers in accordance with one embodiment of the present invention.

Claims

1. A semiconductor memory device, comprising:

2. The semiconductor memory device according to claim 1, wherein the distance between the first gate electrode layer and the second gate electrode layer on the side adjacent the load transistors is shorter than the distance between the first gate electrode layer and the second gate electrode layer on the other side adjacent the driver transistors.

3. The semiconductor memory device according to claim 2, wherein a source contact layer for the load transistors is located adjacent to end sections of the first and second gate electrode layers on the side adjacent the load transistors, and

4. The semiconductor memory device according to claim 2, wherein a distance between the first gate electrode layer and the second gate electrode layer on the side adjacent the load transistors is a minimum value on the design rule.

5. The semiconductor memory device according to claim 2, wherein the load transistors are p-channel type.

6. The semiconductor memory device according to claim 2, wherein a source contact layer for the driver transistors is located in a gate electrode interlayer region defined by a region between the first gate electrode layer and the second gate electrode layer.

7. The semiconductor memory device according to claim 1, further comprising first and second drain-drain connection layers and first and second drain-gate connection layers, wherein

8. The semiconductor memory device according to claim 7, wherein

9. The semiconductor memory device according to claim 7, wherein the first drain-drain connection layer and the second drain-drain connection layer have linear patterns, and

10. The semiconductor memory device according to claim 1, wherein the memory cell has a size of 4.5 m

2 or less.