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Semiconductor memory and its test method

Imported: 23 Feb '17 | Published: 22 Oct '02

Takashi Utsumi, Kiyoshi Adachi

USPTO - Utility Patents

Abstract

A semiconductor memory includes a test memory cell block and a test memory cell selector. The test memory cell block includes a plurality of memory cells that store bit values opposite to each other in adjacent memory cells. The test memory cell selector varies the potential of precharged bit lines by asserting one of the word lines of the test memory cell block, and selects as a memory cell to be tested, a memory cell that is connected to a bit line between the bit lines that changes their potentials in the test memory cell block. It can solve a problem of a conventional semiconductor memory in that it is very difficult to test the function of a circuit installed for suppressing the interference between adjacent bit lines.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a configuration of an embodiment 1 of the semiconductor memory in accordance with the present invention;

FIG. 2 is a block diagram showing a configuration of an embodiment 2 of the semiconductor memory in accordance with the present invention;

FIG. 3 is a block diagram showing a configuration of an embodiment 3 of the semiconductor memory in accordance with the present invention;

FIG. 4 is a block diagram showing a configuration of a source potential modifying means;

FIG. 5 is a circuit diagram showing a configuration of a conventional semiconductor memory (mask ROM);

FIG. 6 is a timing chart illustrating the read operation of the semiconductor memory of FIG. 5;

FIG. 7 is a circuit diagram showing a configuration of a mask ROM as a conventional semiconductor memory with a leaker;

FIG. 8 is a timing chart illustrating the read operation of the semiconductor memory of FIG. 7;

FIG. 9 is a circuit diagram showing a configuration of a mask ROM as a conventional semiconductor memory with a discharger; and

FIG. 10 is a timing chart illustrating the read operation of the semiconductor memory of FIG.

9.

Claims

1. A semiconductor memory comprising:

2. The semiconductor memory according claim 1, further comprising a test memory cell block including a plurality of memory cells placed at individual intersection points of the plurality of bit lines and at least two word lines that are arranged in a matrix fashion, in which the memory cells adjacent to each other store bit values opposite to each other,

3. The semiconductor memory according to claim 2, wherein at least one of a gate width and a gate length of the memory cells of said test memory cell block is greater than those of the memory cells constituting said memory cell block.

4. The semiconductor memory according to claim 2, wherein said test memory cell selector asserts the word line of said test memory cell block by a potential higher than a potential used in an actual operation.

5. The semiconductor memory according to claim 1, wherein said means for precharging consists of a precharge circuit for precharging all the bit lines simultaneously, and said test memory cell selector selects a memory cell that is connected to a bit line between the bit lines precharged by said precharge circuit from said memory cell block as the memory cell to be tested.

6. The semiconductor memory according to claim 1, further comprising a test memory cell block including a plurality of memory cells placed at individual intersection points of the plurality of bit lines and at least two word lines that are arranged in a matrix fashion, in which the memory cells adjacent to each other store bit values opposite to each other,

7. The semiconductor memory according to claim 1, wherein said means for precharging precharges the bit lines up to a potential higher than a potential used in an actual operation.

8. The semiconductor memory according to claim 1, wherein said test memory cell selector asserts the word line of said memory cell block by a potential higher than a potential used in an actual operation.

9. The semiconductor memory according to claim 1, further comprising source potential modifying means for bringing a source potential of the transistors constituting said memory cells to a potential equal to or less than a ground level.

10. A test method of a semiconductor memory including a memory cell block having a plurality of memory cells placed at individual intersection points of a plurality of word lines and a plurality of bit lines that are arranged in a matrix fashion, and an inter-bit-line interference suppression circuit connected to the plurality of bit lines, for releasing potentials of bit lines adjacent to a memory cell whose data is to be read among the memory cells of said memory cell block, thereby suppressing electrical interference between the bit lines, said test method of a semiconductor memory comprising the steps of:

11. The test method of the semiconductor memory according to claim 10, wherein said semiconductor memory further comprises a test memory cell block including a plurality of memory cells placed at individual intersection points of the plurality of bit lines and at least two word lines that are arranged in a matrix fashion, in which the memory cells adjacent to each other store bit values opposite to each other, and wherein the step of asserting produces the potential changes of the precharged bit lines by asserting one of the word lines of said test memory cell block, and selects a memory cell connected to a bit line between the bit lines with their potentials changed from said test memory cell block as the memory cell to be tested.

12. The test method of the semiconductor memory according to claim 10, wherein the step of precharging precharges all the bit lines simultaneously, and the step of asserting selects a memory cell that is connected to a bit line between the precharged bit lines from said memory cell block as the memory cell to be tested.

13. The test method of the semiconductor memory according to claim 10, wherein said semiconductor memory further comprises a test memory cell block including a plurality of memory cells placed at individual intersection points of the plurality of bit lines and at least two word lines that are arranged in a matrix fashion, in which the memory cells adjacent to each other store bit values opposite to each other, and wherein the step of precharging precharges all the bit lines simultaneously, and the step of asserting produces the potential changes of the precharged bit lines by asserting one of the word lines of said test memory cell block, and selects a memory cell connected to a bit line between the bit lines with their potentials changed from said test memory cell block as the memory cell to be tested.