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Semiconductor high dielectric constant decoupling capacitor structures and process for fabrication

Imported: 24 Feb '17 | Published: 24 Aug '04

Howard Hao Chen, Louis L. Hsu, Li-Kong Wang

USPTO - Utility Patents

Abstract

Apparatus and method for providing high dielectric constant decoupling capacitors for semiconductor structures. The high dielectric constant decoupling capacitor can be fabricated by depositing high dielectric constant material between adjacent conductors on the same level, between conductors in successive levels, or both, to thereby provide very large capacitance value without any area or reliability penalty.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will now be described in greater detail with specific reference to the appended drawings wherein:

FIG. 1 shows a typical hysteresis I-V switching loop for a PZT ferroelectric film and operating characteristics therefor;

FIG. 2A shows a first alternative prior art implementation of a planar on-chip capacitor;

FIG. 2B shows a second alternative prior art implementations of a deep trench on-chip capacitor;

FIGS. 3A through 3C provide schematic views of lateral decoupling capacitor in accordance with the present invention;

FIGS. 4A through 4G provide side cutaway views of a process flow for fabricating the structure of FIG. 3C;

FIG. 5 provides a side perspective view of an alternative vertical embodiment of a decoupling capacitor in accordance with the present invention;

FIG. 6 provides a top view of a semiconductor structure in accordance with the present invention, which includes lateral decoupling capacitors both between adjacent interconnect lines on a level and vertical decoupling capacitors between interconnect levels;

FIGS. 7A through 7F provide illustration of a process flow for fabricating the on-chip decoupling capacitor of FIG. 3A;

FIGS. 8A through 8K provide illustration of a process flow for fabricating the on-chip decoupling capacitor of FIG. 5; and

FIG. 9 provides a side perspedctive view of an alternative vertical embodiment of a decoupling capacitor with multiple successive layers in accordance with the present invention.

Claims

1. A semiconductor structure comprising:

2. The semiconductor structure of claim 1, wherein at least one successive conductor level comprising at least one conductor is provided over the adjacent conductors, further comprising second high dielectric constant material disposed between at least one of the adjacent conductors and the at least one successive conductor level.

3. The semiconductor structure of claim 2 wherein at least one pair of adjacent conductors comprises a pair of metal lines.

4. The semiconductor structure of claim 3 wherein the at least one successive conductor level comprises a first successive level comprising at least one conductive via electrically coupled to at least one of the pair of metal lines.

5. The semiconductor structure of claim 4 wherein the at least one successive conductor level additionally comprises a second conductor level comprising additional adjacent conductors disposed above the first successive level.

6. The semiconductor structure of claim 5 wherein the second conductor level additionally comprises third high dielectric constant material disposed between the additional adjacent conductors.

7. The semiconductor structure of claim 6 further comprising at least one electrically conductive barrier material disposed between the third high dielectric constant material and the additional adjacent conductors.

8. The semiconductor structure of claim 2 further comprising at least one electrically conductive barrier material disposed between the second high dielectric constant material and the at least one conductor.

9. The semiconductor structure of claim 1 wherein the high dielectric constant material is selected from the group consisting of ferroelectrics, relaxors, paraelectrics, perovskites, pyrochlores, layered perovskites or any material with a dielectric constant which is greater than 10.

10. The semiconductor structure of claim 1 wherein the conductors are fabricated from at least one of the group consisting of Au, Pt, Pd, Ir, Rh, Ru, Mo, Al, Cu, W, their alloys, and doped polysilicon.

11. The semiconductor structure of claim 1 further comprising a diffusion barrier material formed between said high dielectric constant material and said conductors.

12. The semiconductor structure of claim 11 wherein the diffusion barrier material is selected from the group consisting of RuO

2, IrO

2, Re

2O

3, TiN, TaN and TaSiN.

13. The semiconductor structure of claim 1 wherein at least one pair of adjacent conductors comprises a power supply line an a ground wire.

14. The semiconductor structure of claim 1 wherein the gap is in the range of 0.1 to 2.0 microns.