BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a cross-sectional view of a conventional semiconductor device of a two-layer wiring structure;
FIGS. 2 through 4 are cross-sectional views for describing a method for manufacturing the semiconductor devise shown in FIG. 1;
FIG. 5 is a cross-sectional view for describing a problem arising in the semiconductor device shown in FIG. 1;
FIG. 6 is a cross-sectional view showing a major part of a semiconductor device according to a first embodiment of the present invention;
FIG. 7 is a diagram for illustrating problems involved in a manufacturing method employed in the first embodiment;
FIG. 8 is a cross-sectional view showing a major part of a semiconductor device according to a second embodiment of the present invention;
FIG. 9 is a cross-sectional view showing a major part of a semiconductor device according to a third embodiment of the present invention;
FIG. 10 is a cross-sectional view showing a major part of a semiconductor device according to a fourth embodiment of the present invention;
FIG. 11 is a cross-sectional view showing a major part of a semiconductor device according to a fifth embodiment of the present invention;
FIG. 12 is a diagram illustrating the major part of a method for manufacturing a semiconductor device according to a sixth embodiment of the present invention;
FIG. 13 is a diagram illustrating the major part of a method for manufacturing a semiconductor device according to a seventh embodiment of the present invention;
FIG. 14 is a diagram illustrating the major part of a method for manufacturing a semiconductor device according to a eighth embodiment of the present invention;
FIG. 15 is a diagram showing a distribution of fluorine concentrations employed in a ninth embodiment of the present invention; and
FIGS. 16A and 16B are diagrams showing a distribution of fluorine concentrations employed in a tenth embodiment of the present invention.