Quantcast

Semiconductor device

Imported: 23 Feb '17 | Published: 22 Oct '02

Hiroyuki Mizuno, Yusuke Kanno, Takao Watanabe

USPTO - Utility Patents

Abstract

A dynamic memory requires refreshing to retain data in its memory cells. This may cause access to the dynamic memory for purposes other than refreshing (external access) and access to it for refreshing to compete with each other, resulting in a performance deterioration. According to this invention, a pipelined dynamic memory. (PDRAM) is used, and the pipeline frequency (CLK) of the pipelined dynamic memory is made higher than the frequency (CLK

1) of external access, and access required for refreshing is made to an unoccupied slot (a timing when any external access request is never issued) in the pipeline of the pipelined dynamic memory. This makes refreshing of the internal dynamic memory an internal operation, which eliminates the need to take refreshing into consideration at the time external access is made, leading to improvement in operating ease and speed.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred embodiments of the present invention will be described in detail based on the followings, wherein:

FIG. 1 illustrates an embodiment according to this invention;

FIGS. 2A and 2B are graphs showing operating waveforms of a conventional dynamic memory;

FIGS. 3A and 3B show an example of operating waveforms of a dynamic memory according to this invention;

FIG. 4 illustrates an embodiment of a dynamic memory based on a direct sensing scheme according to this invention;

FIGS. 5A,

5B and

5C illustrate an embodiment of a pipelined dynamic memory according to this invention and its operating waveforms;

FIGS. 6A,

6B and

6C show an embodiment of a pipelined dynamic memory according to this invention, in which the write latency is identical to the read latency, as well as its operating waveforms;

FIG. 7 shows an embodiment which has a forward circuit in addition to the embodiment shown in FIG. 5A;

FIGS. 8A and 8B show examples of usage of a dynamic memory according to this invention in case where no cache memory can be used;

FIG. 9 illustrates an embodiment of a pipelined dynamic memory;

FIG. 10 illustrates an embodiment of a refresh-free dynamic memory which has an access control circuit to conceal refreshing operation from outside in addition to a pipelined dynamic memory PDRAM;

FIG. 11 is a timing chart for operation of the embodiment shown in FIG. 10;

FIG. 12 illustrates an embodiment of a refresh-free dynamic memory in case where the frequency ratio of CLK

1 and CLK

2 shown in FIG. 10 is 3/2;

FIG. 13 is a timing chart for operation of the embodiment shown in FIG. 12;

FIG. 14 illustrates an embodiment which has a clock generating circuit in addition to the embodiment shown in FIG. 10;

FIG. 15 illustrates an embodiment of a pipelined dynamic memory which uses 3T memory cells; and

FIG. 16 illustrates an embodiment of a merged DRAM/logic LSI which uses a refresh-free dynamic memory according to this invention.

Claims

1. A semiconductor device comprising:

2. A semiconductor device according to claim 1,

3. A semiconductor device according to claim 2,

4. A semiconductor device according to claim 2,

5. A semiconductor device comprising:

6. A semiconductor device according to claim 5,

7. A semiconductor device according to claim 6,

8. A semiconductor device comprising: