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Semiconductor device with programming capacitance element

Imported: 23 Feb '17 | Published: 22 Oct '02

Hideto Hidaka

USPTO - Utility Patents

Abstract

In order to implement a capacitor-type anti-fuse having desired breakdown voltage characteristics and efficiently and reliably set in a blown state while reliably holding program information in a normal operation mode, capacitance elements having the same structure as memory cell capacitors are arranged alignedly along a row or column direction and coupled in parallel with each other for implementing a capacitor-type anti-fuse. The memory cell pattern is repeated also in a peripheral circuit region, whereby capacitance elements having a complete structure can be implemented to implement a capacitor-type anti-fuse correctly having desired characteristics.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 schematically illustrates the overall structure of a semiconductor device according to the present invention;

FIG. 2 schematically illustrates the internal structure of a redundant replacement control circuit shown in FIG. 1;

FIG. 3 illustrates the structure of a programming circuit included in a semiconductor memory device according to an embodiment 1 of the present invention;

FIG. 4 schematically illustrates the internal structure of the programming circuit shown in FIG. 3;

FIG. 5 illustrates the structure of a modification 1 of the embodiment 1 of the present invention;

FIG. 6A illustrates the structure of a modification 2 of the embodiment 1 of the present invention, and FIG. 6B illustrates an electric equivalent circuit of the structure shown in FIG. 6A;

FIG. 7 schematically illustrates the structure of a modification 3 of the embodiment 1 of the present invention;

FIG. 8 schematically illustrates the structure of a modification 4 of the embodiment 1 of the present invention;

FIG. 9A illustrates the structure of a programming element according to an embodiment 2 of the present invention, and FIG. 9B illustrates an electric equivalent circuit of the structure shown in FIG. 9A;

FIG. 10A schematically illustrates the structure of an anti-fuse circuit according to the embodiment 2 of the present invention, and FIG

10B is a signal waveform diagram representing an operation of the anti-fuse circuit shown in FIG. 10A;

FIG. 11A illustrates a cross sectional structure of a programming element according to an embodiment 3 of the present invention, and FIG.

11B schematically illustrates the planar layout of the structure shown in FIG. 11A;

FIG. 12A illustrates a cross sectional structure of a modification 1 of the embodiment 3 of the present invention, and FIG. 12B schematically illustrates the plane layout of the structure shown in FIG. 12A;

FIG. 13 schematically illustrates the structure of a modification 2 of the embodiment 3 of the present invention;

FIG. 14 schematically illustrates the structure of an anti-fuse circuit according to an embodiment 4 of the present invention;

FIG. 15A illustrates an applied voltage in a programming operation mode of the anti-fuse circuit shown in FIG. 14, and FIG. 15B illustrates an electric equivalent circuit of the structure shown in FIG. 15A;

FIG. 16A illustrates an applied voltage in fuse blowing in the circuit shown in FIG. 14, and FIG. 16B illustrates an electric equivalent circuit of the structure shown in FIG. 16A;

FIG. 17A illustrates an applied voltage in a normal operation mode of the circuit shown in FIG. 14, and FIG. 17B illustrates an electric equivalent circuit of the structure shown in FIG. 17A;

FIG. 18 illustrates the structure of a portion generating control signals shown in FIG. 14;

FIG. 19 illustrates the breakdown voltage characteristic of a capacitor according to an embodiment 5 of the present invention;

FIGS. 20A and 20B illustrate asymmetrical breakdown voltage characteristics;

FIG. 21A illustrates the direction of a voltage applied in programming in an embodiment 5 of the present invention, and FIG. 21B illustrates the direction of a voltage applied to a capacitor in a normal operation mode of the embodiment 5 of the present invention;

FIG. 22A illustrates the direction of a voltage applied in programming in an embodiment 6 of the present invention, and FIG. 22B illustrates the direction of a voltage applied to a capacitor in a normal operation mode in the embodiment 6 of the present invention;

FIG. 23A schematically illustrates the structure of an anti-fuse circuit receiving the voltages shown in FIGS. 22A and 22B, and FIG. 23B is a signal waveform diagram representing operations of the circuit shown in FIG. 23A;

FIG. 24 schematically illustrates the structure of a portion generating control signals shown in FIG. 23A;

FIG. 25A schematically illustrates the structure of an anti-fuse circuit according to an embodiment 7 of the present invention, and FIG. 25B is a signal waveform diagram representing operations of the circuit shown in FIG. 25A;

FIG. 26 Schematically illustrates the structure of a control signal generation portion shown in FIG. 25A;

FIG. 27 schematically illustrates the structure of a defect repairing circuit according to an embodiment 8 of the present invention;

FIG. 28 is a flow chart showing a programming procedure in the structure shown in FIG. 27;

FIG. 29 schematically illustrates the structure of an address programming circuit shown in FIG. 27;

FIG. 30 illustrates an exemplary structure of a switching circuit shown in FIG. 27;

FIGS. 31A and 31B illustrate exemplary structures of a spare element selection circuit shown in FIG. 27 respectively;

FIG. 32 is a flow chart showing operations of a modification of the embodiment 8 of the present invention;

FIG. 33, schematically illustrates the structure of a semiconductor device according to an embodiment 9 of the present invention;

FIG. 34 shows a structure of a modification of the embodiment 9;

FIG. 35 illustrates an exemplary structure of a conventional anti-fuse circuit; and

FIG. 36A is a signal waveform diagram representing operations in programming of the circuit shown in FIG. 35, and FIG. 36B is a signal waveform diagram representing operations in a normal operation mode of the circuit shown in FIG.

35.

Claims

1. A semiconductor device comprising:

2. The semiconductor device in accordance with claim 1, wherein

3. The semiconductor device in accordance with claim 2, wherein said plurality of capacitance elements and said plurality of replica transistors are so arranged that unit cells each comprised of a capacitance element and a replica transistor are aligned along the row direction, and

4. The semiconductor device in accordance with claim 2, wherein said plurality of capacitance elements and said plurality of replica transistors are so arranged that unit cells each comprised of a capacitance element and a replica transistor are aligned along the column direction, and

5. The semiconductor device in accordance with claim 1, wherein said programming element further includes a semiconductor substrate region of a first conductivity type arranged in common to said plurality of capacitance elements,

6. The semiconductor device in accordance with claim 2, wherein said plurality of replica transistors are employed in said program control circuit as a decoupling transistor for preventing transmission of a high voltage in a programming operation mode of said programming element.

7. The semiconductor device in accordance with claim 1, wherein each of said plurality of capacitance elements has a storage node and a cell plate node facing to said storage node with an insulation film placed therebetween, said cell plate node is electrically connected to an upper-layer line through a contact hole formed in a portion facing to said storage node, said upper layer line is coupled in common to said plurality of capacitance elements, and the storage nodes of the capacitance elements are electrically connected together.

8. The semiconductor device in accordance with claim 1, wherein said plurality of capacitance elements are grouped into a first programming capacitance element and a second programming capacitance element, and

9. A semiconductor device comprising:

10. The semiconductor device in accordance with claim 9, wherein said first and second impurity regions of said capacitor are the same in conductivity type as said substrate region.

11. A semiconductor device comprising:

12. A semiconductor device comprising:

13. A semiconductor device comprising:

14. A semiconductor device comprising: