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Semiconductor device with an interposer

Imported: 25 Feb '17 | Published: 01 Jul '03

Takashi Saito

USPTO - Utility Patents

Abstract

An improved semiconductor chip interconnection advantageously employs a thin conductive layer that is used to form conductive members located between two nonconductive layers. The upper nonconductive layer has openings formed therein through which electrical connections are made between contacts in the chip member and the conductive members. The conductive members preferably have portions which are substantially parallel to a bottom surface of the semiconductor chip located between nonconductive layers and an upper nonconductive layer has openings formed therein through which electrical connections are made with the semiconductor chip. The conductive members have portions that extend downward away from the bottom surface of the chip.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIG. 1 is a schematic diagram illustrating a state of packaging of a CSP mounted on a mounting substrate according to one embodiment of the invention;

FIGS. 2A to

2B are diagrams illustrating a deformation of external terminals due to thermal stresses applied to the CSP, wherein FIG. 2A depicts a normal state while FIG. 2B depicts a deformed state thereof;

FIGS. 3A to

3C show a fan-in type interposer, wherein FIG. 3A shows a bottom surface thereof, FIG. 3B shows a cross-section thereof, and FIG. 3C shows a cross-section in detail of a portion cut along a line IIIC—IIIC in FIG. 3A;

FIGS. 4A to

4B show an enlarged diagram of FIG. 3C, wherein FIG. 4A shows its initial state prior to bending, and FIG. 4B shows its state after bending;

FIG. 5 is an enlarged perspective view of FIG. 4B;

FIGS. 6A to

6B illustrate a fan-in/out type interposer embodying the invention, wherein FIG. 6A shows a bottom surface thereof, and FIG. 6B shows a cross-section thereof;

FIGS. 7A to

7E are diagrams illustrating steps of manufacturing the interposer embodying the invention;

FIGS. 8A to

8E are diagrams illustrating steps of combining an IC chip and the interposer embodying the invention;

FIG. 9 shows a state of the CSP which is mounted on the mounting substrate according to the invention;

FIG. 10 shows an enlarged portion of section A in FIG. 9;

FIG. 11 shows an example of modifications embodying the invention;

FIG. 12 shows another example of modifications embodying the invention;

FIG. 13 shows still another example of modifications embodying the invention;

FIG. 14 shows still more example of modifications embodying the invention;

FIG. 15 shows still further example of modifications embodying the invention;

FIG. 16 is a diagram illustrating a conventional wire bonding type CSP;

FIG. 17 is a diagram illustrating a conventional flip-chip type CSP;

FIG. 18 is a diagram illustrating a conventional ball grid array type connecting method;

FIG. 19 is a diagram illustrating a conventional land grid array type connecting method;

FIG. 20 is a diagram illustrating a state of packaging of a conventional flip-chip type CSP; and

FIG. 21 is a diagram illustrating a state of breakage of a conventional flip chip type CSP due to a thermal stress after its packaging.

Claims

1. A semiconductor device comprising:

2. The semiconductor device as claimed in claim 3, wherein;

3. An interposer to be affixed and connected to a semiconductor chip as to form a semiconductor package comprising:

4. The interposer as claimed in claim 3, wherein

5. The interposer as claimed in claim 3, wherein

6. The interposer as claimed in claim 3, wherein

7. A semiconductor mounting structure comprising:

8. The semiconductor mounting structure as cited in claim 7, wherein

9. The semiconductor device of claim 1, wherein the portions that extend downward are located between the non-conductive layers.

10. The interposer of claim 3, wherein the portions that extend downward are located between the non-conductive layers.

11. The semiconductor mounting structure of claim 7, wherein the portions that extend downward are located between the non-conductive layers.