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Removable spacer technology using ion implantation to augment etch rate differences of spacer materials

Imported: 25 Feb '17 | Published: 06 Aug '02

Emi Ishida, Srinath Krishnan, Ming Hao, Effiong Ibok

USPTO - Utility Patents

Abstract

Submicron-dimensioned MOS and/or CMOS transistors are fabricated by a process employing removable sidewall spacers made of a material, such as UV-nitride, which has been treated subsequent to its deposition, e.g., by ion implantation, to augment its etch rate with a room temperature etchant, e.g., dilute aqueous HF. The treated spacers are removed with the dilute, aqueous HF after implantation of moderately or heavily-doped source/drain regions but prior to any post-implantation annealing processing, in order not to increase the etch resistance of the spacer material by thermally-induced densification.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS.

1(A)-

1(J) illustrate, in simplified, cross-sectional form, a sequence of processing steps for forming an MOS-type transistor according to an embodiment of the present invention, wherein like reference numerals are employed throughout for designating like features and/or components of the invention.

Claims

1. A method of manufacturing a semiconductor device, which method comprises the steps of:

2. The method as in claim 1, wherein step (b) comprises forming said first, relatively narrow sidewall spacers from a first dielectric material selected from the group consisting of silicon oxides, silicon nitrides, and silicon oxynitrides.

3. The method as in claim 2, wherein each of said first, relatively narrow, tapered sidewall spacers has a width profile varying from up to about 200 Å at the lower end thereof adjacent said substrate surface to up to about 100 Å at the upper end thereof.

4. The method as in claim 1, wherein step (c) comprises forming said second, relatively wider, sidewall spacers from a second dielectric material having an as-deposited etch resistance and selected from the group consisting of UV-nitrides, silicon oxides, silicon nitrides, and silicon oxynitrides.

5. The method as in claim 4, wherein step (c) comprises forming said second, relatively wider, sidewall spacers from a CVD UV-nitride.

6. The method as in claim 1, wherein each of said second, relatively wider, tapered sidewall spacers has a width profile varying from about 100 Å to about 1,000 Å at the lower end thereof adjacent said substrate surface to up to about 400 Å at the upper end thereof.

7. The method as in claim 1, wherein step (d) comprises ion implantation of said second pair of sidewall spacers.

8. The method as in claim 7, wherein step (d) comprises implanting impurity ions selected from Si

+, Ge

+, and p and n type dopant ions at dosages of from about 1×10

14 to about 5×10

15 ions/cm

2 and energies of from about 1 to about 250 KeV.

9. The method as in claim 1, wherein step (e) comprises implanting dopant ions of second opposite conductivity type at dosages of from about 5×10

14 to about 5×10

15 ions/cm

2 and energies of from about 1 to about 250 KeV.

10. The method as in claim 9, wherein step (f) comprises selectively removing the ion-implanted, reduced etching resistance second insulative sidewall spacers by etching with dilute aqueous HF.

11. The method as in claim 10, wherein step (f) comprises etching the second insulative spacers at a removal rate of from about 0.3 to about 5 Å/min. with 1:100 HF/H

2O at about 20-35° C.

12. The method as in claim 1, wherein step (g) comprises rapid thermal annealing to diffuse and activate said second conductivity type dopant impurities introduced during step (e) to form said pair heavily-doped source/drain regions, each having a junction depth of from about 500 Å to about 2,000 Å below the substrate surface.

13. The method as in claim 1, wherein step (h) comprises selectively implanting dopant ions of second conductivity type at dosages of from about 5×10

13 to about 1×10

15 ions/cm

2 and energies of from about 0.2 to about 30 KeV.

14. The method as in claim 1, wherein step (i) comprises rapid thermal annealing to diffuse and activate said second conductivity type dopant impurities introduced during step (h) to form said pair of shallow-depth, lightly- or moderately-doped source/drain extensions, each having a shallow junction depth of from about 100 Å to about 1,000 Å below said substrate surface.

15. The method as in claim 1, comprising performing steps (d) and (e) simultaneously by implanting second conductivity type dopant impurities.

16. A method of manufacturing a silicon-based MOS-type transistor, which method comprises the steps of:

17. The method as in claim 16, wherein step (d) comprises implanting impurity ions selected from Si

+, Ge

+, and p and n type dopant ions at dosages of from about 1×10

14 to about 5×10

15 ions/cm

2 and energies from about 1 to about 250KeV.

18. The method as in claim 17, wherein step (f) comprises etching the second insulative spacers at a removal rate of from about 0.3 to about 5 Å/min. with 1:100 HF/H

2O at about 20-35° C.

19. A method of manufacturing a semiconductor device, which method comprises the steps of:

20. The method as in claim 19, wherein step (b) comprises forming said first and second sidewall spacers from a dielectric material selected form the group consisting of silicon oxides, silicon nitrides, and silicon oxynitrides.

21. The method as in claim 19, wherein step (d) comprises ion implantation of said second pair of sidewall spacers.

22. The method as in claim 19, wherein step (f) comprises selectively removing the ion-implanted, reduced etching resistance second insulative sidewall spacers by etching with dilute aqueous HF.

23. The method as in claim 19, wherein step (g) comprises rapid thermal annealing to diffuse and activate said second conductivity type dopant impurities introduced during step (e) to form said pair heavily-doped source/drain regions, each having a junction depth of from about 500 Å to about 2,000 Å below the substrate surface.

24. The method as in claim 19, comprising performing steps (d) and (e) simultaneously by implanting second conductivity type dopant impurities.

25. The method as in claim 19, wherein step (f) comprises etching the second insulative spacers at a removal rate of from about 0.3 to about 5 Å/min.

26. A method of manufacturing a semiconductor device, which method comprises the steps of:

27. The method as in claim 26, wherein step (b) comprises forming said first and second sidewall spacers form a dielectric material selected from the group consisting of silicon oxides, silicon nitrides, and silicon oxynitrides.

28. The method as in claim 26, wherein step (d) comprises ion implantation of said second pair of sidewall spacers.

29. The method as in claim 28, wherein step (d) comprises implanting impurity ions selected from Si

+, Ge

+, and p and n type dopant ions at dosages of form about 1×10

14 to about 5×10

15 ions/cm

2 and energies of from about 1 to about 250 KeV.

30. The method as in claim 29, wherein step (d) comprises implanting Si

+, Ge

+, ions.

31. The method as in claim 26, wherein step (f) comprises etching the second insulative spacers at a removal rate of from about 0.3 to about 5 Å/min.