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Programmable external graphics/video port for digital video decode system chip

Imported: 23 Feb '17 | Published: 22 Oct '02

Dennis P. Cheney, Lawrence D. Curley, William R. Lee, Leland D. Richardson, Ronald S. Svec

USPTO - Utility Patents

Abstract

A programmable bi-directional external graphics/video (EGV) port for a video decode system chip having a video decoder and an internal digital display generator circuit is provided. The programmable EGV port employs a fixed number of signal input/output (I/O) pins on the video decode system chip while providing a plurality of connection configurations for an external graphics controller, an external digital display generator circuit and an external digital multi-standard decoder to the video decoder or the internal digital display generator circuit of the chip. The EGV port includes receiver/driver circuitry for accommodating in parallel a plurality of input/output signals, including pixel data signals and corresponding synchronization signals, as well as a programmable port controller adapted to be coupled between the receiver/driver circuitry and an internal bus of the video decode system allowing access to at least one of the video decoder and the internal digital display generator circuit. The programmable port controller is programmable to either receive data into the video decode system chip or to send data out from the video decode system chip.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above-described objects, advantages and features of the present invention, as well as others, will be more readily understood from the following detailed description of certain preferred embodiments of the invention, when considered in conjunction with the accompanying drawings in which:

FIG. 1 depicts a general block diagram of a video decode unit;

FIG. 2 is a block diagram of a video decode system chip to employ an external graphics/video (EGV) port in accordance with the principles of the present invention;

FIG. 3 is a block diagram of one example of circuitry for one bit of an EGV port in accordance with the principles of the present invention;

FIG. 4 depicts one connection example for an EGV port in accordance with the principles of the present invention, wherein the EGV port couples an external digital display generator circuit to a video decode system chip of a digital video set-top box;

FIG. 5 depicts another connection example for an EGV port in accordance with the principles of the present invention, wherein an external graphics controller and external digital display generator circuitry are coupled to the video decode system chip;

FIG. 6 is a more detailed depiction of the external graphics controller, external digital display generator circuitry and STB chip connections for the EGV port application of FIG. 5;

FIG. 7 depicts still another connection example for an EGV port in accordance with the principles of the present invention, wherein an external graphics controller is coupled to the video decode system chip;

FIG. 8 is a more detailed depiction of the EGV port application of FIG. 7 showing signal connections between the external graphics controller and the video decode system chip;

FIG. 9 depicts still another connection example for an EGV port in accordance with the principles of the present invention, wherein an external digital multi-standard decoder is connected to the digital video decode system chip;

FIG. 10 depicts another connection example for the EGV port in accordance with the principles of the present invention, showing connection of the external digital multi-standard decoder to both the video decoder and the internal digital display generator circuitry of the video decode system chip;

FIG. 11 is a more detailed block diagram of the EGV port application of FIG. 10;

FIG. 12 is a yet further connection example for an EGV port in accordance with the principles of the present invention, wherein both an external digital multi-standard decoder and an external graphics controller are coupled to the video decode system chip; and

FIG. 13 is a more detailed block diagram of the EGV port application of FIG.

12.

Claims

1. An external graphics/video (EGV) port for a video decode system chip having a video decoder and an internal digital display generator circuit, said EGV port comprising:

2. The EGV port of claim 1, wherein said video decode system chip is employed in at least one of a digital video set-top box, a digital video disc (DVD) player, or a computer enabled with a DVD drive.

3. The EGV port of claim 1, further comprising a plurality of signal input/output (I/O) pins on said video decode system chip, said receiver/driver circuitry being coupled to said plurality of signal I/O pins for accommodating said plurality of input/output signals.

4. The EGV port of claim 3, wherein at least one pin of said plurality of signal I/O pins comprises a sync pin, and wherein said programmable port controller is adapted to either receive for said video decode system chip or send from said video decode system chip the master sync signal for coordinating data flow between said video decoder, said internal digital display generator circuit, and at least one of an external graphics controller, an external digital display generator circuit, and an external digital multi-standard decoder (DMSD).

5. The EGV port of claim 4, wherein said at least one sync pin comprises a horizontal synchronization signal pin and a vertical synchronization signal pin.

6. The EGV port of claim 1, wherein said plurality of input/output signals comprise at least some of: video pixel data signals; said master synchronization signal; a chrominance reference signal; and a clock signal.

7. The EGV port of claim 6, wherein said plurality of input/output signals comprise said video pixel data and said master synchronization signal, and wherein said programmable port controller is programmable to either receive or send said video pixel data and is further independently programmable to either receive or send said master synchronization signal, said master synchronization signal being associated with said video pixel data.

8. The EGV port of claim 1, wherein said programmable port controller is programmed to couple said external digital display generator circuit to said video decoder of said video decode system chip.

9. The EGV port of claim 8, wherein said programmable port controller is programmed to forward video pixel output from said video decoder to said external digital display generator circuit simultaneous with providing said video decoder with said master synchronization signal from said external digital display generator circuit.

10. The EGV port of claim 9, wherein said programmable port controller is programmed to provide in parallel at least eight video pixel output bit lines, a horizontal synchronization signal bit line, a vertical synchronization signal bit line and a chroma reference bit line for coupling said video decoder and said external digital display generator circuit.

11. The EGV port of claim 1, wherein said programmable port controller is programmed to couple said external graphics controller and said external digital display generator circuit to said video decoder of said video decode system chip.

12. The EGV port of claim 11, wherein said programmable port controller is programmed to forward video pixel output from said video decoder to said external graphics controller, and wherein said external graphics controller is adapted to feed video pixel output to said external digital display generator circuit in response to said video pixel output from said video decoder, and wherein said external digital display generator circuit is adapted to provide said video decoder and said external graphics controller with said master synchronization signal for said video pixel output, said master synchronization signal being provided to said video decoder via said EGV port.

13. The EGV port of claim 12, wherein said programmable port controller is programmed to provide a chroma reference signal from said video decoder to said external graphics controller and said external digital display generator circuit along with providing said video pixel output from said video decoder to said external graphics controller and said master synchronization signal from said external digital display generator circuit to said video decoder.

14. The EGV port of claim 1, wherein said programmable port controller is programmed to couple said external graphics controller to said video decoder of said video decode system chip for provision of graphics data for overlaying or blending within said video decoder with video pixel data.

15. The EGV port of claim 14, wherein said programmable port controller is further programmed to forward said master synchronization signal from said internal digital display generator circuit to said external graphics controller along with providing said graphics data to said video decoder from said external graphics controller.

16. The EGV port of claim 15, wherein said programmable port controller is further programmed to forward a chrominance reference signal from said video decoder to said external graphics controller along with providing said graphics data to said video decoder from said external graphics controller and providing said master synchronization signal to said external graphics controller from said internal digital display generator circuit.

17. The EGV port of claim 1, wherein said programmable port controller is adapted to couple said external digital multi-standard decoder (DMSD) to said internal digital display generator circuit.

18. The EGV port of claim 1, wherein said programmable port controller is adapted to couple said external graphics controller and said external digital multi-standard decoder (DMSD) to said video decoder and said internal digital display generator circuit of said video decode system chip.

19. The EGV port of claim 1, wherein said programmable port controller is configurable to any one of multiple configurations of external device connections to at least one of said video decoder and said internal digital display generator circuit of said video decode system chip.

20. The EGV port of claim 19, wherein said multiple configurations comprise:

21. A programmable bidirectional external graphics/video (EGV) port for a video decode system chip having a video decoder and an internal digital display generator circuit, said EGV port comprising:

22. The EGV port of claim 21, wherein said video decode system chip is employed in at least one of a digital video set-top box or a digital video disc player.

23. The EGV port of claim 21, wherein said second programmable logic independently receives on chip or sends off chip two synchronization signals for said video pixel data, said two synchronization signals comprising a horizontal synchronization signal and a vertical synchronization signal.

24. The EGV port of claim 21, wherein said programmable port controller is configurable to any one of multiple configurations of external device connections to at least one of said video decoder and said internal digital display generator circuit of said video decode system chip.

25. The EGV port of claim 24, wherein said multiple configuration comprise: