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Pipelined analog-to-digital converter using zero-crossing capacitor swapping scheme

Imported: 23 Feb '17 | Published: 22 Oct '02

Arlo J. Aude

USPTO - Utility Patents

Abstract

There is disclosed, for use in an analog to digital (ADC) converter, an ADC stage that receives a differential analog input signal, quantizes the differential analog input signal to a plurality of digital bits, and generates an output residue signal corresponding to a quantization error of the differential analog input signal. The ADC stage comprises: 1) a differential amplifier having an inverting input and a non-inverting input and a differential output comprising an inverting output and a non-inverting output; 2) a first capacitor having a first side and a second side and a second capacitor having a first side and a second side, wherein the second side of the first capacitor is coupled to the second side of the second capacitor and to the inverting input of the differential amplifier; 3) a third capacitor having a first side and a second side and a fourth capacitor having a first side and a second side, wherein the second side of the third capacitor is coupled to the second side of the fourth capacitor and to the non-inverting input of the differential amplifier; 4) a switch matrix for coupling the first sides of the first, second, third and fourth capacitors to selected ones of the first sides of the first, second, third and fourth capacitors, to selected ones of the inverting and non-inverting outputs of the differential amplifiers, and to selected ones of a positive reference voltage and a negative reference voltage; and 5) a switch control logic circuit for detecting a zero reference level crossing, wherein a voltage level on a preceding non-inverting output of a preceding ADC stage transitions from below a voltage level on a preceding inverting output of said preceding ADC stage to a voltage level above said voltage level on said preceding inverting output.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, wherein like numbers designate like objects, and in which:

FIG. 1 illustrates an exemplary pipelined analog-to-digital converter (ADC) according to one embodiment of the present invention;

FIG. 2 illustrates the ideal output function of the pipelined ADC in FIG. 1 according to one embodiment of the present invention;

FIG. 3 illustrates a selected portion of an exemplary 1.5 bit stage in the pipelined ADC according to one embodiment of the present invention;

FIG. 4 illustrates logic circuitry that generates the switch control signals that drive the switch architecture in the 1.5 bit stage according to one embodiment of the present invention; and

FIG. 5 illustrates the switch architecture and differential amplifier used to generate the differential output signal of the exemplary 1.5 bit stage according to one embodiment of the present invention.

Claims

1. For use in an analog-to-digital converter (ADC), an ADC stage capable of receiving a differential analog input signal, quantizing said differential analog input signal to a plurality of digital bits, and generating an output residue signal corresponding to a quantization error of said differential analog input signal, said ADC stage comprising:

2. The ADC stage as set forth in claim 1 wherein said switch control logic circuit is capable of controlling said switch matrix.

3. The ADC stage as set forth in claim 2 wherein, prior to detection of said zero-reference level crossing, said switch matrix is set such that said first side of said first capacitor is coupled to said non-inverting output, said first side of said fourth capacitor is coupled to said inverting output, and said first side of said second capacitor is coupled to said first side of said third capacitor.

4. The ADC stage as set forth in claim 3 wherein said switch control logic circuit, in response to detection of said zero-reference level crossing, modifies said switch matrix such that said first side of said first capacitor is coupled to said first side of said fourth capacitor, said first side of said second capacitor is coupled to said non-inverting output, and said first side of said third capacitor is coupled to said inverting output.

5. The ADC stage as set forth in claim 4 wherein said switch control logic circuit is capable of detecting a negative trip point crossing, wherein a voltage level on said preceding non-inverting output transitions from below a negative trip point to above said negative trip point, wherein said negative trip point is below said zero reference level.

6. The ADC stage as set forth in claim 5 wherein said switch control logic circuit is capable of modifying said switch matrix in response to detection of said negative trip point crossing.

7. The ADC stage as set forth in claim 6 wherein said switch control logic circuit is capable of detecting a positive trip point crossing, wherein a voltage level on said preceding non-inverting output transitions from below a positive trip point to above said positive trip point, wherein said positive trip point is above said zero reference level.

8. The ADC stage as set forth in claim 7 wherein said switch control logic circuit is capable of modifying said switch matrix in response to detection of said positive trip point crossing.

9. An analog-to-digital converter (ADC) comprising a plurality of ADC stages, at least one of said ADC stages capable of receiving a differential analog input signal, quantizing said differential analog input signal to a plurality of digital bits, and generating an output residue signal corresponding to a quantization error of said differential analog input signal, said at least one ADC stage comprising:

10. The analog-to-digital converter as set forth in claim 9 wherein said switch control logic circuit is capable of controlling said switch matrix.

11. The analog-to-digital converter as set forth in claim 10 wherein, prior to detection of said zero-reference level crossing, said switch matrix is set such that said first side of said first capacitor is coupled to said non-inverting output, said first side of said fourth capacitor is coupled to said inverting output, and said first side of said second capacitor is coupled to said first side of said third capacitor.

12. The analog-to-digital converter as set forth in claim 11 wherein said switch control logic circuit, in response to detection of said zero-reference level crossing, modifies said switch matrix such that said first side of said first capacitor is coupled to said first side of said fourth capacitor, said first side of said second capacitor is coupled to said non-inverting output, and said first side of said third capacitor is coupled to said inverting output.

13. The analog-to-digital converter as set forth in claim 12 wherein said switch control logic circuit is capable of detecting a negative trip point crossing, wherein a voltage level on said preceding non-inverting output transitions from below a negative trip point to above said negative trip point, wherein said negative trip point is below said zero reference level.

14. The analog-to-digital converter as set forth in claim 13 wherein said switch control logic circuit is capable of modifying said switch matrix in response to detection of said negative trip point crossing.

15. The analog-to-digital converter as set forth in claim 14 wherein said switch control logic circuit is capable of detecting a positive trip point crossing, wherein a voltage level on said preceding non-inverting output transitions from below a positive trip point to above said positive trip point, wherein said positive trip point is above said zero reference level.

16. The analog-to-digital converter as set forth in claim 15 wherein said switch control logic circuit is capable of modifying said switch matrix in response to detection of said positive trip point crossing.

17. A method for use in an analog-to-digital converter (ADC) comprising an ADC stage capable of receiving a differential analog input signal, quantizing the differential analog input signal to a plurality of digital bits, and generating an output residue signal corresponding to a quantization error of the differential analog input signal, the ADC stage comprising: 1) a differential amplifier having an inverting input and a non-inverting input and a differential output comprising an inverting output and a non-inverting output; 2) a first capacitor having a first side and a second side and a second capacitor having a first side and a second side, wherein the second side of the first capacitor is coupled to the second side of the second capacitor and to the inverting input of the differential amplifier; 3) a third capacitor having a first side and a second side and a fourth capacitor having a first side and a second side, wherein the second side of the third capacitor is coupled to the second side of the fourth capacitor and to the non-inverting input of the differential amplifier; 4) a switch matrix capable of coupling the first sides of the first, second, third and fourth capacitors to selected ones of the first sides of the first, second, third and fourth capacitors, to selected ones of the inverting and non-inverting outputs of the differential amplifiers, and to selected ones of a positive reference voltage and a negative reference voltage, the method comprising the steps of:

18. The method as set forth in claim 17 wherein in the first state, prior to detection of the zero-reference level crossing, the switch matrix is set such that the first side of the first capacitor is coupled to the non-inverting output, the first side of the fourth capacitor is coupled to the inverting output, and the first side of the second capacitor is coupled to the first side of the third capacitor.

19. The method as set forth in claim 18 wherein in the second state, in response to detection of the zero-reference level crossing, the switch matrix is set such that the first side of the first capacitor is coupled to the first side of the fourth capacitor, the first side of the second capacitor is coupled to the non-inverting output, and the first side of the third capacitor is coupled to the inverting output.

20. The method as set forth in claim 19 further comprising the steps of detecting a negative trip point crossing, wherein a voltage level on the preceding non-inverting output transitions from below a negative trip point to above the negative trip point, wherein the negative trip point is below the zero reference level.

21. The method as set forth in claim 20 further comprising the step of modifying the switch matrix in response to detection of the negative trip point crossing.

22. The method as set forth in claim 21 further comprising the step of detecting a positive trip point crossing, wherein a voltage level on the preceding non-inverting output transitions from below a positive trip point to above the positive trip point, wherein the positive trip point is above the zero reference level.

23. The method as set forth in claim 22 further comprising the step of modifying the switch matrix in response to detection of the positive trip point crossing.