Parallel phase locked loops skew measure and dynamic skew and jitter error compensation method and apparatus

A method and apparatus for skew measure and dynamic skew and jitter error compensation. A plurality of programmable delay lines corresponding to a plurality of signals is provided, wherein each delay line is in a path of a corresponding signal. A skew measure circuit is configured to receive at least two signals to be synchronized. The skew measure circuit determines a phase difference between the at least two signals. The skew measure circuit is coupled to the programmable delay lines and uses the phase difference to program at least one of the delay lines to delay at least one of the signals to be synchronized such that the signals are in synchronization.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a plurality of circuits, each circuit being a phase locked loop circuit;

FIG. 2 is a timing diagram showing skewed jitter error introduced in the PLLs of the above Figure;

FIG. 3 is a schematic diagram of a plurality of PLL circuits in which a skew measure circuit and programmable delay devices have been implemented in accordance with one embodiment of the invention;

FIG. 4 is a schematic diagram of an exemplary skew measure circuit in accordance with an embodiment of the invention;

FIG. 5 is a timing diagram that aids in the understanding of the skew measure circuit shown in FIG. 4;

FIG. 6 is a schematic diagram of an exemplary programmable delay device in accordance with an embodiment of the invention;

FIG. 7 is a schematic diagram of a plurality of PLL circuits in which a skew measure circuit and programmable delay devices have been implemented in accordance with another embodiment of the invention;

FIG. 8 is a timing diagram that aids in the understanding of the circuit shown in FIG. 7;

FIG. 9 is a schematic diagram of an average circuit of the type which may be used in connection with the circuit of FIG. 7;

FIG. 10 is a flow chart that shows a method of dynamically compensating for skew and jitter errors between synchronous clock circuits in accordance with an embodiment of the invention.

1. An apparatus comprising:

2. The apparatus as in claim 1, wherein the skew measure circuit comprises:

3. The apparatus as in claim 2, wherein the skew measure circuit further comprises:

4. The apparatus as in claim 3, wherein the duration of the enablement of the logic circuit is a duration of a delay programmed into the enabled programmable delay line by the skew measure circuit.

5. The apparatus as in claim 3, wherein the skew measure circuit further comprises a reset circuit to reset the first latch and the second latch when both latches are enabled.

6. A method comprising:

7. The method as in claim 6, wherein the step of determining which signal is leading, further comprises:

8. The method as in claim 7, wherein the step of determining a phase difference further comprises:

9. The method as in claim 8, further comprising:

10. The method as in claim 8, further comprising:

11. A system comprising:

12. The system as in claim 11, wherein the skew measure circuit comprises;

13. The system as in claim 12, wherein the skew measure circuit further comprises:

14. The system as in claim 13, wherein the duration of the enablement of the logic circuit is the duration of the delay programmed into the enabled programmable delay line by the skew measure circuit.

15. The system as in claim 13, wherein the skew measure circuit further comprises a reset circuit to reset the first latch and the second latch when both latches are enabled.

16. A system comprising:

17. The system defined by claim 16 wherein said at least first and second average circuits each comprise: