Indexed on: 04 Jun '10Published on: 04 Jun '10Published in: Journal of Electronic Testing
Scan-based testing of integrated circuits results in significant switching activity during the shift operations, dissipating excessive power levels. When such levels are beyond the peak power level under which the chip can functionally operate at, it may lead to an unexpected behavior of the design, resulting in a yield loss. One of the most effective solutions to reduce peak shift power is to partition the scan chains into multiple groups, wherein a single group is active at any time instance within a shift cycle. The partitioning of the chains into groups can be performed statically, i.e., per test set, or dynamically, i.e., per test pattern. In this work, we address the application of dynamic scan chain partitioning for reducing peak shift power. First, we address the application of dynamic partitioning to test delay faults in at-speed test techniques. Then, we formulate the scan chain partitioning problem via Integer Linear Programming (ILP), in order to evenly distribute the transitions produced by any pattern over multiple time instances within the shift cycle, maximally reducing the peak shift power. Finally, we evaluate the power reduction benefit of dynamic partitioning through an extensive set of experiments using different scan configurations and test set characteristics of benchmark circuits as well as industrial designs. The results indicate that dynamic partitioning provides significant reduction to peak shift power over static partitioning methods, and that the benefit is accentuated in scan architectures with fewer scan chains, test sets with more don’t care bits, and designs with larger variances of weight differences for transitions in the scan cells.