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Non-volatile semiconductor memory device capable of preventing program disturb due to noise voltage induced at a string select line and program method thereof

Imported: 25 Feb '17 | Published: 06 Apr '04

Jae-Yong Jeong, Sung-Soo Lee

USPTO - Utility Patents

Abstract

Disclosed is a non-volatile semiconductor memory device including a circuit for controlling potentials of select lines and word lines in accordance with bit line setup, string select line setup, program and discharge periods of a program cycle. The control circuit biases a string select line to a power supply voltage during the bit line setup period in the program cycle, and to a voltage between the power supply voltage and ground voltage during the string select line setup and the program periods. According to the string select line control scheme, program disturb due to a noise voltage induced at a string select line when a program voltage is applied to a word line adjacent to the string select line is prevented.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings in which:

FIG. 1 is a circuit diagram showing a configuration of an array in a general flash memory device;

FIG. 2 is a timing diagram showing a programming operation according to the conventional art;

FIG. 3 is a block diagram showing a flash memory device according to a preferred embodiment of the present invention;

FIG. 4 is a string select line control unit shown in FIG. 1; and

FIG. 5 is a timing diagram showing a programming operation according to a preferred embodiment of the present invention.

Claims

1. A method of programming in a non-volatile semiconductor memory device having a memory cell array formed of a plurality of cell strings each of which is connected through a first and second select transistor between a bit line and a common source line and each of which includes a plurality of cell transistors, formed in a pocket P-well, control gates of each memory cell transistor being respectively coupled to a word line arranged in parallel between a first and second select line, the method comprising the steps of:

2. The method of claim 1, wherein the first voltage is a power supply voltage and the second voltage is a ground voltage.

3. The method of claim 1, wherein the third voltage is sufficient to turn on the first select transistor connected to the bit line corresponding to a data bit to be programmed.

4. The method of claim 1, wherein the third voltage is between a fourth and fifth voltage, wherein the fourth voltage is sufficient to turn on the first select transistor connected to the bit line corresponding to the data bit to be programmed, and the fifth voltage is a shut-off voltage of the first select transistor for the bit line corresponding to the data bit to be program inhibited, the shut-off voltage being determined by the first voltage—(×Vpgm), wherein is a coupling ratio of the word line to the string select line, and wherein Vpgm is the program voltage.

5. The method of claim 1, wherein the third voltage is a voltage corresponding to a threshold voltage of a N-channel metal oxide semiconductor (NMOS) transistor or to a sum of the threshold voltages of plural NMOS transistors.

6. The method of claim 1, wherein the bit line setup operation is long enough to raise the bit line corresponding to a data bit to be programmed to the first voltage.

7. The method of claim 1, wherein the string select line setup operation occurs in an interval between completion of the bit line setup operation and completion of a program operation.

8. The method of claim 1, wherein the bit line corresponding to the data bit to be program inhibited is electrically isolated from the cell string corresponding thereto after the bit line setup operation, and a channel voltage of a memory cell transistor, connected to a select word line, corresponding to the data bit to be program inhibited is self-boosted higher than the first voltage when the program voltage is applied to the select word line.

9. The method of claim 8, wherein the self-boosting operation includes a local self-boosting operation.

10. The method of claim 9, wherein the self-boosting operation is achieved by applying a pass voltage to the unselect word line and by applying the ground voltage to the unselect word line adjacent to the select word line before applying the program voltage to the select word line.

11. The method of claim 9, wherein the self-boosting operation is achieved by applying a pass voltage to the unselect word line and by applying the ground voltage to the two unselect word lines adjacent to the select word line before applying the program voltage to the select word line.

12. The method of claim 9, wherein the self-boosting operation is achieved by applying a first pass voltage to all the word lines and by concurrently applying the program voltage and a second pass voltage to the select and unselect bit lines, wherein the first pass voltage is lower than the second pass voltage.

13. The method of claim 9, wherein the self-boosting operation is achieved by applying a first pass voltage to all the word lines, by applying a second pass voltage higher than the first pass voltage to the unselect word line, and by applying the ground voltage to the unselect word line adjacent to the select word line before applying the program voltage to the select word line.

14. The method of claim 9, wherein the self-boosting operation is performed by applying a first pass voltage to all the word lines, by applying a second pass voltage higher than the first pass voltage to the unselect word line, and by applying the ground voltage to the two unselect word lines adjacent to the select word line before applying the program voltage to the select word line.

15. The method of claim 1, wherein the bit line corresponding to the data bit to be program inhibited is electrically isolated from the cell string corresponding thereto after the bit line setup operation, and wherein a pass voltage lower than the program voltage is applied to the unselect word lines for a channel voltage of memory cell transistors of the cell string corresponding to the program inhibit data bit to be self-boosted when the program voltage is applied to the select word line.

16. A method of programming in a non-volatile semiconductor memory device having a memory cell array formed of a plurality of cell strings each of which is connected through a first and second select transistors between a bit line and a common source line and has a plurality of cell transistors, formed in a pocket P-well, having control gates of the memory cell transistor being respectively coupled to a word line arranged in parallel between a first and second select line, method comprising the steps of:

17. The method of claim 16, wherein the first voltage is a power supply voltage, and the second voltage is a ground voltage.

18. The method of claim 16, wherein the third voltage is sufficient to turn on the first select transistor connected to the bit line corresponding to the data bit to be programmed.

19. The method of claim of

16, wherein the third voltage is between a fourth and fifth voltage, wherein the fourth voltage is sufficient to turn on the first select transistor connected to the bit line corresponding to the data bit to be programmed, and wherein the fifth voltage is a shut-off voltage of the first select transistor for the bit line corresponding to the data bit to be program inhibited, the shut-off voltage being determined by the first voltage—(×Vpgm), wherein is a coupling ratio of the word line to the string select line, and wherein Vpgm is the program voltage.

20. The method of claim 16, wherein the third voltage is a voltage corresponding to a sum of threshold voltages of one or more NMOS transistors.

21. A non-volatile semiconductor memory device comprising:

22. The device of claim 21, wherein the first voltage is a power supply voltage, and the second voltage is a ground voltage.

23. The device of claim 21, wherein the third voltage is sufficient to turn on the string select transistor connected to the bit line corresponding to the data bit to be programmed.

24. The device of claim 21, wherein the third voltage is between a fourth and fifth voltages, wherein the fourth voltage is sufficient to turn on the first select transistor connected to the bit line corresponding to the data bit to be programmed, and wherein the fifth voltage is a shut-off voltage of the first select transistor for the bit line corresponding to the data bit to be program inhibited, the shut-off voltage being determined by the first voltage—(×Vpgm), wherein is a coupling ratio of the word line to the string select line and wherein Vpgm is the program voltage.

25. The device of claim 21, wherein the third voltage is substantially twice a threshold voltage of NMOS transistor.

26. A method of programming in a non-volatile semiconductor memory device having a memory cell array formed of a plurality of cell strings each of which is connected through a first and second select transistor between a bit line and a common source line and each of which includes a plurality of cell transistors, formed in a pocket P-well, control gates of each memory cell transistor being respectively coupled to a word line arranged in parallel between a first and second select line, the method comprising the steps of:

27. A method of programming in a non-volatile semiconductor memory device having a memory cell array formed of a plurality of cell strings each of which is connected through a first and second select transistors between a bit line and a common source line and has a plurality of cell transistors, formed in a pocket P-well, having control gates of the memory cell transistor being respectively coupled to a word line arranged in parallel between a first and second select line, method comprising the steps of:

28. A non-volatile semiconductor memory device comprising:

29. A non-volatile semiconductor memory device comprising: