Quantcast

Non-volatile semiconductor memory device and manufacturing method thereof

Imported: 23 Feb '17 | Published: 22 Oct '02

Kiyoteru Kobayashi, Naoki Tsuji

USPTO - Utility Patents

Abstract

A non-volatile semiconductor memory device allowing accurate reading of data, having superior charge detection characteristic and high rewriting durability, and free of undesirable writing of a non-selected memory cell transistor is provided. A memory cell transistor

100

b includes a silicon substrate

1 having a main surface, a plurality of strip shaped isolating oxide films

4

a and

4

b formed on the main surface

1

b of silicon substrate

1 to continuously extend approximately along the <

100> direction, and strip shaped source and drain regions

5

b and

6

b formed on the main surface

1

b of silicon substrate

1 to continuously extend approximately along the <

100> direction.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view of the EEPROM in accordance with the present invention.

FIG. 2 is a cross sectional view taken along the line II—II (in the direction of word lines) of FIG.

1.

FIG. 3 is a cross sectional view taken along the line III—III (in the direction of data lines) of FIG.

1.

FIG. 4 is cross sectional view showing a peripheral region of the EEPROM shown in FIG.

1.

FIG. 5 is a plan view of a silicon substrate used for the description of the first step of manufacturing the EEPROM shown in FIGS. 1 to

3.

FIGS. 6,

8,

10 and

12 are cross sections taken along the direction of word lines representing the second to fifth steps of manufacturing the EEPROM shown in FIGS. 1 to

3.

FIGS. 7,

9,

11 and

13 are cross sections taken along the direction of data lines representing the second to fifth steps of manufacturing the EEPROM shown in FIGS. 1 to

3.

FIG. 14 is a plan view representing the sixth step of manufacturing the EEPROM shown in FIG.

1.

FIG. 15 is a cross section taken along the line XV—XV of FIG.

14.

FIG. 16 is a cross section taken along the line XVI—XVI of FIG.

14.

FIGS. 17,

19,

21,

23,

25 and

27 are cross sections taken along the direction of word lines representing the seventh to twelfth steps of manufacturing the EEPROM shown in FIGS. 1 to

3.

FIGS. 18,

20,

22,

24,

26, and

28 are cross sections taken along the direction of data lines representing the seventh to twelfth steps of manufacturing the EEPROM shown in FIGS. 1 to

3.

FIG. 29 is a cross section of a conventional EEPROM.

Claims

1. A non-volatile semiconductor memory device, comprising:

2. The non-volatile semiconductor memory device according to claim 1, wherein said control gate electrode includes a plurality of control gate electrodes formed continuously extending along a certain direction, and direction of extension of said isolating insulation films and said impurity regions is approximately orthogonal to the certain direction along which said control gate electrodes extend.