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Multi-level type nonvolatile semiconductor memory device

Imported: 23 Feb '17 | Published: 22 Oct '02

Hirotomo Miura, Yasuo Sato

USPTO - Utility Patents

Abstract

A nonvolatile semiconductor memory device having nonvolatile memory cells, each of said memory cells including a semiconductor substrate of one type of electric conduction, a pair of source and drain regions of the opposite type of electric conduction formed in the semiconductor substrate, an electric charge-capturing film formed on a channel region between the pair of source and drain regions, and a gate electrode formed on the charge-capturing film and working as a control electrode. The electric charge-capturing film has a multi-layer structure in which at least four insulating films and at least three dielectric films each working as an electric charge accumulation layer are alternatingly laminated one upon the other, the lowermost insulating film among the at least four insulating films is formed as a gate-insulating film, a plurality of different threshold voltages are set to the at least three dielectric films to correspond to their electric charge-capturing states, and at least four kinds of memory states are specified depending upon the plurality of threshold voltages. This constitution makes it possible to easily and reliably adjust the amount of electric charge to be captured and, hence, to store desired multi-value data while preventing the occurrence of an inconvenience such as data corruption.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a sectional view schematically illustrating the constitution of a major portion of a nonvolatile semiconductor memory device according to an embodiment of the present invention;

FIGS. 2

a to

2

e are diagrams of steps for illustrating a method of producing the nonvolatile semiconductor memory device of the embodiment of FIG. 1;

FIG. 3 is a diagram illustrating a method of writing data according to the embodiment of FIG. 1;

FIG. 4 is a flow chart illustrating the method of writing data;

FIG. 5 is a diagram illustrating a method of reading data according to the embodiment of FIG. 1;

FIG. 6 is a flow chart illustrating the method of reading data;

FIG. 7 is a sectional view schematically illustrating the constitution of a modified example of the embodiment of FIG. 1;

FIG. 8 is a sectional view schematically illustrating the constitution of another modified example of the embodiment of FIG. 1;

FIGS. 9

a to

9

c are diagrams schematically illustrating the constitution of a major portion of the nonvolatile semiconductor memory device according to another embodiment of the present invention; and

FIGS. 10

a to

10

e are diagrams of steps to illustrate a method of producing the nonvolatile semiconductor memory device of the embodiment of FIGS. 9

a to

9

c.

Claims

1. A semiconductor memory device having memory cells, wherein:

2. A semiconductor memory device having memory cells, wherein:

3. A semiconductor memory device having memory cells, wherein: