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Multi-level dram trench store utilizing two capacitors and two plates

Imported: 25 Feb '17 | Published: 06 Aug '02

Toshiharu Furukawa, David V. Horak, Howard L. Kalter

USPTO - Utility Patents

Abstract

A multi-level memory cell capable of storing two or three bits of digital data occupies only four lithographic squares and requires only one or two logic level voltage sources, respectively. High noise immunity derives from integration of the multi-level signal in the memory cell directly from logic level digital signals applied to two capacitors (as well as the bit line for the eight level mode of operation) by using capacitors having different values in order to avoid digital-to-analog conversion during writing. The capacitors can be simultaneously written and read to reduce memory cycle time. Transistor channels and capacitor connections are formed on adjacent semiconductor pillars using plugs of semiconductor material between pillars as common gate structures and connections. Opposite surfaces of the pillars also serve as storage nodes with common capacitor plates formed by conformal deposition between rows of plugs and pillars.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawings, in which:

FIG. 1 is a schematic diagram of a memory cell circuit in accordance with the invention,

FIG. 2A is a truth table explaining the possible stored charge states for writing of the memory cell circuit of FIG. 1 operated as an eight level store,

FIG. 2B is a truth table explaining the possible stored charge states for writing of the memory cell circuit of FIG. 1 operated as a four level store,

FIG. 2C is a write and read/rewrite timing diagram for the truth table of FIG. 2A,

FIG. 2D is a write and read/rewrite timing diagram for the truth table of FIG. 2B, version

2,

FIGS. 3A and 3B are perspective, exploded views of a preferred form of the memory cell of FIG. 1,

FIGS. 4 and 5 are plan (also referred to as “top-down” or “layout”) views of two practical embodiments of a multi-level memory including the memory cell of FIG. 3,

FIGS. 6,

7,

8,

9,

10,

11,

12,

13,

14 and

15 are plan views illustrating fabrication of a multi-level memory in accordance with the invention,

FIGS. 6A,

7A,

8A,

9A,

10A,

11A,

12A,

13A,

14A and

15A are cross-sectional views along section A—A of FIGS. 6-15, respectively, and

FIGS. 6B,

7B,

8B,

9B,

10B,

11B,

12B,

13B,

14B and

15B are cross-sectional views along section B—B of FIGS. 6-15, respectively.

Claims

1. A method of making a multilevel memory having transistors formed of pillars and adjacent plugs separated from said pillars by a gate oxide, said method including steps of

2. A method as recited in claim 1, including the further step of

3. A method as recited in claim 2, including the further steps of

4. A method as recited in claim 3, wherein said step of forming capacitors include the steps of

5. A method of making a multilevel memory having transistors formed of pillars and adjacent plugs separated from said pillars by a gate oxide, said method including steps of

6. A method as recited in claim 5, including the further steps of

7. A method as recited in claim 6, wherein said step of forming capacitors include the steps of

8. A method of making a multilevel memory having transistors formed of pillars and adjacent plugs separated from said pillars by a gate oxide, said method including steps of

9. A method as recited in claim 8, wherein said step of forming capacitors include the steps of

10. A method of making a multilevel memory having transistors formed of pillars and adjacent plugs separated from said pillars by a gate oxide, said method including steps of