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Metal oxide semiconductor transistor circuit and semiconductor integrated circuit using the same

Imported: 23 Feb '17 | Published: 22 Oct '02

Shinji Toyoyama, Yuichi Sato

USPTO - Utility Patents

Abstract

A select circuit switches a connection from a gate terminal of an NMOS transistor or a substrate voltage terminal to a semiconductor substrate or well by a Select signal. At this time, a voltage of the substrate voltage terminal is set to be lower than a gate voltage in an OFF state. Consequently, when the semiconductor substrate or well is connected to the gate terminal in an active state, the off-current can be reduced to 10

−10 A/m. When the substrate voltage terminal is connected to the semiconductor substrate or well in a standby state, the off-current can be further reduced to 10

−12 A/m. Thus, leakage currents in the standby state and leakage currents flowing from the power supply voltage terminal to the ground voltage terminal in an active state can be suppressed.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention, and wherein:

FIG. 1 is a circuit diagram of a MOS transistor circuit according to the present invention;

FIG. 2 shows the relationship between gate voltages and drain currents of the NMOS transistor in FIG. 1;

FIG. 3 is a circuit diagram of a CMOS inverter circuit constituted by using the MOS transistor circuit shown in FIG. 1;

FIG. 4 is a detailed circuit diagram of the select circuit in FIG. 3;

FIG. 5 is a circuit diagram of a circuit generating a Selectp signal and a Selectn signal in FIG. 4;

FIG. 6 is a circuit diagram of a conventional NMOS transistor circuit for reducing off-currents;

FIG. 7 shows the relationship between gate voltages and drain currents of the NMOS transistor in FIG. 6;

FIG. 8 is a circuit diagram of a CMOS inverter circuit constituted by using the MOS transistor circuit shown in FIG. 6;

FIG. 9 is a circuit diagram of a MOS transistor circuit for reducing off-currents different from the one shown in FIG. 6;

FIG. 10 shows the relationship between gate voltages and drain currents of the NMOS transistor in FIG. 9; and

FIG. 11 is a circuit diagram of a CMOS inverter circuit constituted by using the MOS transistor circuit shown in FIG.

9.

Claims

1. A MOS transistor circuit comprising: