Manufacturing method of a liquid crystal display

It is intended to provide a manufacturing method of a liquid crystal display that can reduce the manufacturing cost by decreasing the number of masks. A gate insulating film, a semiconductor film, and a silicon nitride film are laid on a substrate on which a gate bus line is formed, back exposure is performed by using the gate bus line as a mask, and the silicon nitride film is then patterned, whereby a channel protective film is formed along the gate bus line. Two device isolation holes are formed over the gate bus line at two locations that are on both sides of a source electrode and a drain electrode and that are separated from each other in the extending direction of the gate bus line. A thin-film transistor is formed in such a manner that a semiconductor active film is formed by a portion of the semiconductor film that is interposed between the two device isolation holes and is thereby electrically isolated from other pixel regions and that a gate electrode is formed by a portion of the gate bus line that is located between the two device isolation holes.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view of an array substrate of a vertical electric field type liquid crystal display panel manufactured by a liquid crystal display manufacturing method according to a first embodiment of the present invention;

FIGS. 2A-2F to

7A-

7F show first to sixth stages, respectively, of the liquid crystal display manufacturing method according to the first embodiment of the invention in which FIGS. 2A,

3A,

4A,

5A,

6A and

7A are substrate sectional views taken along line A-A′ in FIG. 1, FIGS. 2B,

3B,

4B,

5B,

6B, and

7B are substrate sectional views taken along line B-B′ in FIG. 1, FIGS. 2C,

3C,

4C,

5C,

6C, and

7C are substrate sectional views taken along line C-C′ in FIG. 1, FIGS. 2D,

3D,

4D,

5D,

6D, and

7D are substrate sectional views taken along line D-D′ and E-E′ in FIG. 1, FIGS. 2E,

3E,

4E,

5E,

6E, and

7E are substrate sectional views taken along line F-F′ in FIG. 1, and FIGS. 2F,

3F,

4F,

5F,

6F, and

7F are substrate sectional views taken along line G-G′ in FIG. 1;

FIG. 8 is a plan view of an array substrate of a horizontal electric field type liquid crystal display panel manufactured by a liquid crystal display manufacturing method according to a second embodiment of the invention;

FIGS. 9A-9E to

13A-

13E show first to fifth stages, respectively, of the liquid crystal display manufacturing method according to the second embodiment of the invention in which FIGS. 9A,

10A,

11A,

12A, and

13A are substrate sectional views taken along line K-K′ in FIG. 8, FIGS. 9B,

10B,

11B,

12B, and

13B are substrate sectional views taken along line H-H′ in FIG. 8, FIGS. 9C,

10C,

11C,

12C, and

13C are substrate sectional views taken along line I-I′ in FIG. 8, FIGS. 9D,

10D,

11D,

12D, and

13D are substrate sectional views taken along line J-J′ in FIG. 8, and FIGS. 9E,

10E,

11E,

12E, and

13E are substrate sectional views taken along line L-L′ in FIG. 8;

FIG. 14 is a plan view of a conventional vertical electric field type liquid crystal display panel;

FIGS. 15A and 15B to FIGS. 20A and 20B show first to sixth stages, respectively, of a manufacturing method of the conventional vertical electric field type liquid crystal display panel of FIG. 14 in which FIGS. 15A,

16A,

17A,

18A,

19A, and

20A are substrate sectional views taken along line M-M′ in FIG.

14 and FIGS. 15B,

16B,

17B,

18B,

19B, and

20B are substrate sectional views taken along line N-N′ in FIG. 14;

FIG. 21 is a plan view of a conventional horizontal electric field type liquid crystal display panel; and

FIG. 22 is a substrate sectional view taken along line P-P′ in FIG.

21.

1. A manufacturing method of a liquid crystal display, comprising the steps of:

2. The manufacturing method according to claim 1, further comprising the steps of:

3. The manufacturing method according to claim 2, further comprising the step of forming device isolation holes in the vicinity of terminal portions of the respective gate bus lines or terminal portions of the respective storage capacitor lines.