Indexed on: 01 Nov '14Published on: 01 Nov '14Published in: Analog Integrated Circuits and Signal Processing
A novel low voltage tunable linear transconductor is presented. The approach is based on quasi-floating gate transistors achieving higher transconductance and better dc common mode rejection than previous implementations. A dynamic biasing technique improves the sensibility of the linearity to process variations. Measurement results of the circuit, designed in a 0.5 μm CMOS process from 1.4 V power supply, confirm the advantages of the proposed approach with a very high speed operation of 50 MHz of gain-bandwidth product, a IM3 of −40 dB and a nominal power consumption of only 490 μW.