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Low phase noise ring-type voltage controlled oscillator

Imported: 23 Feb '17 | Published: 22 Oct '02

Liang Dai, Ramesh Harjani

USPTO - Utility Patents

Abstract

A delay stage used in a ring-type voltage-controlled oscillator has an inverter, a memory element, and tuning circuitry. The memory element is coupled to the output of the inverter to delay the time before the inverter's output begins to switch states in response to the inverter's input switching states. The tuning circuitry receives a control voltage and is coupled to the inverter to alter the strength of the inverter without altering the strength of the memory element. Altering the strength of the tuning circuitry alters the delay of the delay stage, and hence the frequency of the VCO's operation. Because the strength of the memory element is not altered, the speed at which the inverter's output switches remains substantially constant at all tuned frequencies. The switching speed is primarily dictated by the F

T of the process.

Description

DESCRIPTION OF DRAWINGS

FIG. 1 is a block diagram of a PLL circuit that may embody some aspects of the invention.

FIG. 2 is a block diagram of a ring-type VCO circuit, in accordance with an embodiment of the invention, for use with the PLL circuit of FIG.

1.

FIG. 3 is a schematic diagram of a delay stage for the circuit of FIG. 2, in accordance with an embodiment of the invention.

FIGS. 4 and 5 is a timing diagram illustrating the operation of the FIG. 3 circuit.

FIG. 6 is a schematic diagram of an alternative embodiment of a delay stage for the circuit of FIG. 2, in accordance with the invention.

FIG. 7 is a schematic diagram of a second alternative embodiment of a delay stage for the circuit of FIG. 2, in accordance with the invention.

Like reference symbols in the various drawings indicate like elements.

Claims

1. A ring-type voltage-controlled oscillator comprising a plurality of delay stages with delays dependent upon a received control voltage, wherein at least one of the delay stages comprises:

2. The ring-type voltage-controlled oscillator of claim 1, wherein:

3. The ring-type voltage controlled oscillator of claim 2, wherein the tuning circuit comprises a MOS transistor operating as a variable resistor coupled in series with the CMOS inverter, wherein varying the control voltage received at the gate of the MOS transistor varies the voltage drop from source to source across the CMOS inverter at a time when the signal received by the inverter is changing status.

4. A delay stage for a CMOS ring-type voltage-controlled oscillator, the delay stage comprising:

5. The delay stage of claim 4, wherein:

6. The delay stage of claim 4, wherein:

7. The delay stage of claim 4, wherein the memory element comprises first and second PMOS transistors, the gate of the first PMOS transistor coupled to the drain of the second PMOS transistor and also to the second differential output signal, the gate of the second PMOS transistor coupled to the drain of the first PMOS transistor and also to the first differential output signal, and the sources of the first and the second PMOS transistors coupled together and tied to the power supply voltage.

8. The delay stage of claim 4, wherein the memory element comprises first and second NMOS transistors, the gate of the first NMOS transistor coupled to the drain of the second NMOS transistor and also to the second differential output signal, the gate of the second NMOS transistor coupled to the drain of the first NMOS transistor and also to the first differential output signal, and the sources of the first and the second NMOS transistors coupled together and tied to ground voltage.

9. The delay stage of claim 4, wherein the memory element comprises first and second PMOS transistors, the gate of the first PMOS transistor coupled to the drain of the second PMOS transistor and also to the second differential output signal, the gate of the second PMOS transistor coupled to the drain of the first PMOS transistor and also to the first differential output signal, and the sources of the first and the second PMOS transistors coupled together and tied to the power supply voltage; and