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Low noise and low power switched biased CSA with clocked reset and minimal PVT variation for APD based positron emission tomography

Research paper by Ananda Sankar Chakraborty, Sabir Ali Mondal; Hafizur Rahaman

Indexed on: 21 Aug '16Published on: 01 Sep '16Published in: Analog Integrated Circuits and Signal Processing



Abstract

Abstract Switched biased technique is applied to implement a low noise and low power charge-sensitive amplifier (CSA) for avalanche photo-diode (APD) based positron emission tomography front-end application specific integrated circuit, designed in UMC 180 nm CMOS process. This technique pushes MOSFET to the verge of accumulation region during operating time, to reduce 1/f noise and power consumption. APD dark current compensation circuit is implemented with slow Trans-conductance (G-m) feedback loop to compensate up to 200 nA of dark current. Input and output reset functionality is implemented using NMOS switches coupled with dummy transistors. The CSA uses a core amplifier having dc gain of 60 dB, 144 kHz of minimum -3db bandwidth and 345 µW of maximum power consumption with 3.3 V supply voltage. The CSA converts 5–50pC of input charge to 0–2.6 V output while achieving 354pV of input RMS noise and 34e– equivalent noise charge. Replica biasing technique is used to achieve minimal process, voltage, temperature variation in CSA. The complete design of CSA uses 105 µm × 220 µm of layout area.AbstractSwitched biased technique is applied to implement a low noise and low power charge-sensitive amplifier (CSA) for avalanche photo-diode (APD) based positron emission tomography front-end application specific integrated circuit, designed in UMC 180 nm CMOS process. This technique pushes MOSFET to the verge of accumulation region during operating time, to reduce 1/f noise and power consumption. APD dark current compensation circuit is implemented with slow Trans-conductance (G-m) feedback loop to compensate up to 200 nA of dark current. Input and output reset functionality is implemented using NMOS switches coupled with dummy transistors. The CSA uses a core amplifier having dc gain of 60 dB, 144 kHz of minimum -3db bandwidth and 345 µW of maximum power consumption with 3.3 V supply voltage. The CSA converts 5–50pC of input charge to 0–2.6 V output while achieving 354pV of input RMS noise and 34e– equivalent noise charge. Replica biasing technique is used to achieve minimal process, voltage, temperature variation in CSA. The complete design of CSA uses 105 µm × 220 µm of layout area.m–