Low-level circuit implementation of signal flow graphs for real-time signal processing of high-speed digital signals

Signal processing techniques are applied to data rates at state-of-the-art circuit speeds (presently 1.6 Gbit/sec) by carrying out the signal flow graph of a cannonical FIR filter algorithm using hybrid analog and digital circuit techniques. A plurality of digital to analog converters (DACs) generate analog currents that are the analogue of the tap coefficients of the FIR filter model. The DACs are used as programmable current sources for the tail current sources of respective differential pair stages. Differential delay signals that are the analogue of the FIR delay-line tap signals are connected to the inputs of respective ones of the differential pair stages. The drains of the input devices of the differential pair stages are connected in parallel to common complementary load circuits. The delay signals act to steer the tap coefficient currents to one or the other of the common load circuits. The parallel connection to common load circuits acts to sum the currents sunk (if any) by each of the commonly connected input devices. This current summation is the analogue of the FIR accumulator. Because the tap coefficient currents are readily programmable, the filter may be adaptive. An illustrative embodiment uses the invention in a transceiver for high-speed full-duplex (bi-directional simultaneous) signaling over a single channel interconnect. An adaptation algorithm is used at system initialization to train the tap coefficients according to the particular channel characteristics. The invention enables reliable extraction of receive-signals from the inherent ringing induced by the channel interconnect and at higher data rates than previously possible.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 shows a prior-art canonical linear predictive system.

FIG. 2 is an abstract diagram of the system of the present invention.

FIG. 3 is a top-level diagram of the circuit of the present invention.

FIG. 4 is a circuit diagram corresponding to the summer

2100 of FIG.

3.

FIG. 5 is a circuit diagram corresponding to the summer

2200 (also referred to as the echo canceller) of FIG.

3.

FIG. 6 shows a prior-art canonical signal flow graph of a finite impulse response filter.

FIG. 7 is an exemplary sketch illustrating the signal ringing that occurs on the point-to-point channel interconnect.

FIG. 8 is a block diagram that includes the multiplexer and delay functions contained within the filter sub-block

2350 of FIG. 3 as well as a multiplexer and calibration switch responsible for generating the input

2210 that drives summer

2100, also of FIG.

3. The delay functionality roughly corresponds to the tapped delay line of FIG.

6.

FIG. 9 is a circuit diagram of the multiplexer and switch responsible for generating the input

2210 that drives summer

2100 of FIG.

3.

FIG. 10 is a circuit diagram of the multiplexer and delay functions of FIG.

8.

FIG. 11 is a more detailed circuit diagram of the multiplexer of FIGS. 9 and 10.

FIG. 12 shows the correspondence between the coefficient multiplier of FIG. 6 and a differential pair with a programmable current source, according to the present invention.

FIG. 13 is a circuit diagram applying the technique of FIG. 12 to implement the coefficient multiplier and accumulator functions of FIG.

6.

FIG. 14 is a block diagram of the programmable current sources associated with the circuit of FIG.

13.

FIG. 15 is a circuit diagram of corresponding to each of the programmable current sources of FIG.

14.

1. A chip-to-chip interface comprising:

2. The chip-to-chip interface of claim 1 wherein the first signal and the second signal form a full-duplex signal on the connection, and:

3. The chip-to-chip interface of claim 1 wherein:

4. The chip-to-chip interface of claim 3 wherein first transceiver and the second transceiver are configured to initiate the initiation process in response to power-up.

5. A method of operating a chip-to-chip interface where a connection couples a first chip to a second chip, the method comprising;

6. The method of claim 5 wherein the first signal and the second signal form a full-duplex signal on the connection, and:

7. The method of claim 5 wherein:

8. The method of claim 7 further comprising initiating the initiation process in response to power-up.

9. A transceiver for a first chip that is coupled to a second chip by a connection wherein the first chip is configured to transfer a first signal to the second chip over the connection, the second chip is configured to transfer a second signal to the first chip over the connection, and the first signal and the second signal form a full-duplex signal on the connection, the transceiver comprising:

10. The transceiver of claim 9 wherein the circuitry comprises:

11. The transceiver of claim 9 wherein the circuitry includes a filter configured to process the first signal based on tap coefficients to predict the first signal echo, and the circuitry is configured to adaptively set the first tap coefficients during an initialization process when the first chip is transmitting a test signal and the second chip is not transmitting.

12. The transceiver of claim 11 wherein the circuitry is configured to initiate the initiation process in response to power-up.

13. A method of operating a transceiver for a first chip that is coupled to a second chip by a connection wherein the first chip transfers a first signal to the second chip over the connection, the second chip transfers a second signal to the first chip over the connection, and the first signal and the second signal form a full-duplex signal on the connection, the transceiver comprising:

14. The method of claim 13 wherein processing the first signal to predict the first signal echo and removing the first signal and the predicted first signal echo from the full-duplex signal comprises:

15. The method of claim 13 wherein processing the first signal to predict the first signal echo comprises using filter configured to process the first signal based on tap coefficients to predict the first signal echo, and further comprising adaptively setting the first tap coefficients during an initialization process when the first chip is transmitting a test signal and the second chip is not transmitting.

16. The method of claim 15 further comprising initiating the initiation process in response to power-up.