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Integrated ESD protection circuit using a substrate triggered lateral NPN

Imported: 23 Feb '17 | Published: 22 Oct '02

E. Ajith Amerasekera, Charvaka Duvvury

USPTO - Utility Patents

Abstract

An ESD protection circuit (

100) and method is described herein. A lateral npn transistor (

104) is connected between an I/O pad (

110) and ground (GND). A substrate biasing circuit (

150) increases the voltage across a substrate resistance (

114) during an ESD event by conducting current through the substrate. This, in turn, triggers the lateral npn (

104) which clamps to voltage at the pad (

110) and dissipated the ESD current. The lateral npn (

104) is the primary protection device for dissipating ESD current.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings:

FIG. 1 is a schematic diagram of a prior art ESD protection circuit;

FIG. 2 is a schematic diagram of a prior art dual-diode ESD protection circuit;

FIG. 3 is a partially cross-section/partly schematic diagram of an ESD protection device according to one embodiment of the invention;

FIG. 4 is a partially cross-section/partly schematic diagram of an ESD protection device according to the invention having a diode string;

FIG. 5 is a schematic diagram of an ESD protection device according to the invention including a Darlington circuit;

FIG. 6 is a graph of applied voltage versus number of diodes for various vertical pnp transistor gains;

FIG. 7 is a schematic diagram of an ESD protection device according to the invention including a snubber circuit for reducing reverse leakage current;

FIG. 8 is a schematic diagram of an ESD protection device according to the invention including emitter base resistors in a Darlington circuit for increasing the maximum clamp voltage and reducing the reverse leakage current;

FIG. 9 is a schematic diagram of an ESD protection device according to the invention illustrating a Darlington circuit and multiple lateral npn transistors;

FIG. 10 is a exemplary layout diagram of an ESD protection device according to the invention;

FIG. 11 is a preferred layout of an ESD protection device according to the invention;

FIG. 12 is a schematic diagram of a first alternative embodiment of the invention; and

FIG. 13 is a schematic diagram of a second alternative embodiment of the invention.

Claims

1. An ESD protection circuit formed in a substrate comprising:

2. The ESD protection circuit of claim 1, wherein said diode comprises:

3. The ESD protection circuit of claim 2, further comprising an inherent silicon-controlled rectifier (SCR) formed of said p-type diffused region, said well region, said substrate, and an emitter region of said lateral npn transistor.

4. The ESD protection circuit of claim 1 wherein said diode comprises a Darlington string of diodes connected between an I/O pad and a supply voltage.

5. The ESD protection circuit of claim 4, wherein said lateral npn comprises a plurality of npn transistors each having a collector connected to said I/O pad, an emitter connected to a ground potential, and a base connected to said ground potential through an inherent resistance in said substrate.

6. The ESD protection circuit of claim 4, further comprising a reverse diode connected in parallel with said Darlington string of diodes for leakage reduction.

7. The ESD protection circuit of claim 4, further comprising at least one resistor connected between an emitter and base of at least one diode in said Darlington string of diodes.

8. The ESD protection circuit of claim 4, wherein said Darlington string of diodes comprises between 2 and 12 diodes.

9. An ESD protection device located in a substrate, comprising:

10. The ESD protection circuit of claim 9, wherein each of said plurality of pn diodes comprises:

11. The ESD protection circuit of claim 10, further comprising at least one inherent silicon-controlled rectifier (SCR) formed of said p-type diffused region and said well region of one of said plurality of pn diodes, said substrate, and a diffused emitter region of one of said plurality of lateral npn transistors.

12. The ESD protection circuit of claim 9, further comprising a reverse diode connected in parallel with said plurality of pn diodes.

13. The ESD protection circuit of claim 9, further comprising at least one resistor connected between said n-type diffused region and said p-type diffused region of at least one diode of said plurality of pn diodes for balancing the current in said pn diodes of said plurality of pn diodes and for increasing the clamp voltage for mixed voltage operation.

14. A method for ESD protection of internal circuitry at an input/output pad comprising the steps of:

15. The method of claim 14 further comprising the step of triggering an inherent silicon-controlled rectifier (SCR) under ESD conditions comprised of at least one pn diode and said at least one lateral npn transistor.

16. The method of claim 13, wherein said SCR clamps a voltage level at said input/output pad on the order of 4.5 V.

17. The method of claim 15, wherein a holding voltage of the SCR is tunable.

18. The method of claim 14, wherein said conducting ESD current step occurs when a voltage level at said input/output pad reaches on the order of 0.8 V.

19. The method of claim 14 wherein said at least one lateral npn transistors clamps a voltage level at said input/output pad to on the order of 5-7 V.