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Integrated circuit memory device having interleaved read and program capabilities and methods of operating same

Imported: 23 Feb '17 | Published: 22 Oct '02

Cheng-Chung Tsao, Tien-ler Lin

USPTO - Utility Patents

Abstract

A nonvolatile semiconductor memory includes a plurality of memory cells arranged in columns and rows, a plurality of word lines, a plurality of bit lines, a plurality of output buffers, and a plurality of page buffers grouped in a plurality of sub-pages. Each page buffer is connected to corresponding bit lines through a first column decoder circuit and connected to one corresponding output buffer through a second column decoder circuit. This construction allows the peripheral control circuits to clock out data stored in page buffers of a first sub-page into output buffers while latching bit line data into page buffers of a second sub-page. Therefore, this architecture is able to perform read and update the page buffer data of different sub-pages simultaneously. Two sets of address registers are used to store the starting and the end address for programming. During programming, only sub-pages located between the starting and end address will be programmed successively. This sub-page programming technique greatly reduces the disturbance and programming time.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic layout of a floor plan of an integrated memory circuit device of the present invention.

FIG. 2A is a schematic diagram showing the connection of the bit lines to page buffers and the grouping of page buffers into sub-pages in the device of the present invention.

FIG. 2B is a schematic diagram showing the connection of the metal strapping to VSS.

FIG. 3 is a detailed schematic circuit diagram showing the connections between the page buffers and bit-lines, and the connections from page buffers to output buffers of the device of the present invention.

FIG. 3A is a detailed circuit diagram showing the bit-line pre-charge circuits of the device of the present invention.

FIG. 3B is a detailed circuit diagram showing the data line pre-charge circuits of the device of the present invention.

FIG. 3C is a circuit diagram showing a sense amplifier and the read-modify-write circuit associated with each page buffer of the device of the present invention.

FIG. 4 is a detailed circuit diagram showing the connection of a page buffer to a first and a second column decoder circuits

FIG. 4A is a timing diagram for page-mode read operation for the device of the present invention.

FIG. 4B is a detailed circuit diagram showing the connection between bit-lines and output buffers.

FIG. 4C is a timing diagram for page-mode program operation for the device of the present invention.

FIG. 4D is a circuit diagram showing the generation of the signal BIASR used in the circuit shown in FIG.

4.

FIG. 5 is a schematic block diagram of the device of the present invention.

FIG. 6 is a timing chart showing the page-mode read operation for the device of the present invention.

FIG. 7 is a flow chart showing the sub-page pre-fetch operation in the page mode read method of the present invention.

FIG. 8 is a flow chart showing the sub-page programming operation in the page mode program method of the present invention

Claims

1. An integrated circuit memory device for emulating the read operation of a NAND memory device, said integrated circuit memory device comprising:

2. The device of claim 1 wherein each of said plurality of sub-pages of memory cells comprises a plurality of non-adjacent evenly spaced bit lines with memory cells coupled thereto, with said plurality of sub-pages of memory cells interleaving one another.

3. The device of claim 2 wherein each sub-page buffer is associated with a plurality of adjacent bit lines; and

4. The device of claim 3 wherein each sub-page buffer is associated with two bit lines.

5. The device of claim 4 wherein each sub-page buffer further comprises:

6. An integrated circuit memory device for emulating the programming operation of a NAND memory device, said integrated circuit memory device comprising:

7. The device of claim 6, further comprising:

8. The device of claim 6 wherein each of said plurality of sub-pages of memory cells comprises a plurality of non-adjacent evenly spaced bit lines with memory cells coupled thereto, with said plurality of sub-pages of memory cells interleaving one another.

9. The device of claim 8 wherein each sub-page buffer is associated with a plurality of adjacent bit lines; and

10. The device of claim 9 wherein each sub-page buffer is associated with two bit lines.

11. The device of claim 10 wherein each sub-page buffer further comprises: