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High-precision D-A converter circuit

Imported: 23 Feb '17 | Published: 22 Oct '02

Norihide Kinugasa, Kenichi Tatehara

USPTO - Utility Patents

Abstract

The digital-analog converter circuit includes: a high-order D-A converter circuit unit (

100) for outputting a first voltage (Va) and a second voltage (Vb) both resulting from D-A conversion of the high-order five bits of a 13-bit input code to first and second output nodes (

11, 12) through two buffers (

10

a,

10

b) having the same characteristics, respectively; a low-order D-A converter circuit unit (

200) for receiving the voltages on these two output nodes as reference voltages of an R-2R ladder circuit (

201) and conducting D-A conversion of the low-order eight bits of the input code for output to a third output node (

13); a sample-and-hold unit (

250) for selectively sampling and holding the voltage on the third output node (

13), i.e., the D-A conversion output of the 13-bit input code, according to a value of the input code; and an output unit (

300) for multiplying the sampled and held D-A conversion output voltage by a gain with respect to an arbitrary central voltage. Thus, a D-A converter circuit capable of outputting a desired analog voltage with high accuracy even when a large number of bits are converted is implemented with a small chip area.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing the basic structure of a composite D-A converter circuit according to an embodiment of the present invention;

FIG. 2 is a diagram showing the circuit structure of a control unit of the D-A converter circuit of FIG. 1;

FIG. 3 is an operating waveform chart of a main part of the control unit of FIG. 2;

FIG. 4 is a diagram showing the structure of a simultaneous ON prevention circuit for preventing a plurality of non-adjacent MOS switches in a high-order D-A converter circuit unit of FIG. 1 from being simultaneously turned ON;

FIG. 5 is a diagram specifically showing the circuit structure of the high-order D-A converter circuit unit of FIG. 1;

FIG. 6 is a diagram showing the structure of a circuit for controlling a substrate voltage of each MOS switch in the high-order D-A converter circuit unit of FIG. 1;

FIG. 7 is an operating waveform chart of a main part of the high-order D-A converter circuit unit of FIG. 1;

FIG. 8 is a diagram showing the circuit structure of a low-order D-A converter circuit unit of FIG. 1;

FIG. 9 is a diagram showing the structure of a circuit or controlling a substrate voltage of each MOS switch in the low-order D-A converter circuit unit of FIG. 1;

FIG. 10 is an operating waveform chart of a main part of the low-order D-A converter circuit unit of FIG. 1;

FIG. 11 is a diagram showing the circuit structure of a sample-and-hold unit of FIG. 1;

FIG. 12 is a diagram showing the circuit structure of a sample-and-hold signal producing unit;

FIG. 13 is an operating waveform chart of a main part of the sample-and-hold signal producing unit of FIG. 12;

FIG. 14 is a diagram showing the circuit structure of an output unit of FIG. 1;

FIG. 15 is an operating waveform chart of a main part of the output unit of FIG. 14;

FIG. 16 is a diagram showing an output waveform when a clear signal is applied to the output unit of FIG. 14;

FIGS. 17A and 17B are diagrams illustrating the layout of string resistances in the high-order D-A converter circuit unit of FIG. 1;

FIG. 18 is a diagram showing the circuit structure of a resistance string unit having dummy resistances provided at both ends of the string resistances of FIG. 1;

FIG. 19 is a diagram showing the layout of an R−2R ladder resistance unit in the low-order D-A converter circuit unit of FIG. 1;

FIG. 20 is a block diagram showing the basic structure of a D-A converter including a plurality of composite D-A converter circuits of FIG. 1;

FIG. 21 is a diagram showing the circuit structure of an initializing unit of FIG. 20;

FIG. 22 is a diagram showing the circuit structure of an output unit in the composite D-A converter circuit of FIG. 20; and

FIG. 23 is an operating waveform chart of a main part in FIGS. 20 to

22.

Claims

1. A digital-analog converter circuit, characterized in that comprises:

2. The digital-analog converter circuit according to claim 1, characterized in that the high-order D-A converter circuit unit includes:

3. The digital-analog converter circuit according to claim 1, characterized in that the high-order D-A converter circuit unit includes:

4. The digital-analog converter circuit according to claim 1, characterized in that the high-order D-A converter circuit unit includes:

5. The digital-analog converter circuit according to claim 4, characterized in that it further comprises a means for switching a substrate voltage supplied to an n-channel MOS transistor and a p-channel MOS transistor of each of the first and second switch means and the MOS resistances to the two reference voltages according to the odd/even detection signal.

6. The digital-analog converter circuit according to claim 1, characterized in that the high-order D-A converter circuit unit includes:

7. The digital-analog converter circuit according to claim 6, characterized in that the sample-and-hold signal producing unit includes:

8. The digital-analog converter circuit according to claim 1, characterized in that the output unit includes a switch means, wherein when a clear signal is applied as a control input and the sample-and-hold unit holds the voltage on the third node, a voltage multiplied by a gain with respect to an arbitrary central voltage is applied to a feedback input terminal of an operational amplifier, and a voltage having the same voltage difference from the central voltage with respect to a ground potential as that of the voltage applied to the feedback input terminal is applied from the switch means to an input terminal of the operational amplifier.

9. The digital-analog converter circuit according to claim 1, characterized in that the high-order D-A converter circuit unit includes:

10. The digital-analog converter circuit according to claim 1, characterized in that the high-order D-A converter circuit unit includes:

11. The digital-analog converter circuit according to claim 1, characterized in that n, i and j are 13, 5 and 8, respectively.

12. A multi-channel D-A converter including a plurality of digital-analog converter circuits according to any one of claims

1,

2,

3, and

4 to

10, characterized in that it comprises: