Quantcast

High bandwidth 3D memory packaging technique

Imported: 23 Feb '17 | Published: 22 Oct '02

William F. Beausoleil, Edmund D. Blackshear, Michael J. Ellsworth, Jr., William F. Shutler, Norton J. Tomassetti

USPTO - Utility Patents

Abstract

A three-dimensional memory module in a repetitively used pedestal connector provides signal paths unique and common to the module at its level and signal paths from the level below unique to and common to modules at levels above. In order to provide a unique signal path from a substrate to each memory module, while using identical pedestal connectors at each level, signal lines are skewed from where they enter the bottom surface of the pedestal connector to where they exit the top surface. For example, each input in a line of inputs is connected to a matching line of outputs, but with a shift of one position between input and output.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other features and advantages of the invention will be described with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. Also in the figures, the left most digit of each reference number corresponds to the figure in which the reference number is first used.

FIG. 1 is a schematic diagram of one embodiment of the invention.

FIG. 2 is a side view of one embodiment of a pedestal connector used in FIG.

1.

FIG. 3 is a plan view of the pedestal connector shown in FIG.

2.

FIG. 4 is a schematic diagram to illustrate the three-dimensions in which connections are made.

FIG. 5 is a schematic diagram similar to FIG. 1 illustrating an alternate connector pattern.

FIG. 6 is a fragmentary, sectional view of the conductor paths implemented in a multi-layer ceramic module technology.

FIG. 7 is a side view of another embodiment of a pedestal connector.

FIG. 8 is a side view of still another embodiment of a pedestal connector.

FIG. 9 is a plan view of the pedestal connector shown in FIG.

8.

FIG. 10 illustrates a conductor path that can provide a common connection to all modules.

Claims

1. A three-dimensional array of modules comprising in combination:

2. A three-dimensional array of modules comprising in combination:

3. A three-dimensional array of modules comprising in combination: