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Flash memory device capable of preventing program disturb and method for programming the same

Imported: 23 Feb '17 | Published: 22 Oct '02

Sun-Mi Choi, Yeong-Taek Lee, Young-Ho Lim

USPTO - Utility Patents

Abstract

Disclosed is a method for programming a non-volatile semiconductor memory device that avoids the program disturb problem. In the programming method, ground voltage is applied to a first bit line corresponding to a memory cell to be programmed, and power supply voltage is applied to a second bit line corresponding to a memory cell to be prevented from being programmed. Next, a program voltage is applied to a word line connected to the memory cell to be programmed. The program voltage is stepped up to a desired voltage level of each program cycle from the first voltage thereby to reduce coupling between selected and non-selected bit and word lines.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings in which:

FIG. 1 is a graph showing variation of a program voltage employed in a programming operation according to a preferred embodiment of the present invention;

FIG. 2 is a block diagram showing a flash memory device according to the preferred embodiment of the present invention;

FIG. 3 is a circuit diagram showing a memory block shown in FIG. 2;

FIG. 4 is a block diagram showing a selection signal generator relative to a predetermined word line according to the preferred embodiment of the present invention;

FIG. 5 is a circuit diagram showing a clock driver shown in FIG. 4;

FIG. 6 is a circuit diagram showing a voltage divider shown in FIG. 4;

FIG. 7 is a timing diagram showing control signals employed in the selection signal generator shown in FIG. 4; and

FIGS. 8A and 8B are graphs showing variations in the program voltage in response to output signals of a decoder shown in FIG.

4.

Claims

1. A method for programming a non-volatile memory device having a plurality of memory cells arranged in matrix, a first and second selection transistors for selecting a memory cell, a plurality of bit lines connected to drains of the memory cells, and a plurality of word lines connected to control gates of the memory cells, the method comprising the steps of:

2. The method of claim 1, the method further comprising a step of applying a pass voltage to all of the word lines except for the first word line.

3. The method of claim 1, the method further comprising a step of applying the first voltage to a second word line adjacent to the first word line and the pass voltage to the other word lines except the first and second word lines.

4. The method of claim 1, wherein the first voltage is a ground voltage, and the second voltage is a power supply voltage.

5. A NAND-type flash memory device comprising:

6. The device of claim 5, wherein the selection signal generating circuit comprises:

7. A NAND-type flash memory device comprising:

8. The device of claim 7, wherein the control signals provided from the decoder are activated during a period corresponding to one cycle of the clock signal.