Imported: 23 Feb '17 | Published: 22 Oct '02
USPTO - Utility Patents
An electrostatic discharge protective circuit can receive a pre-stage driver output and involve a first PMOS transistor, a first NMOS transistor and a second NMOS transistor and all connect in series. More particularly, a source region of the first PMOS transistor connects to a system power source; and a drain region connects to a conductive pad, and a gate receives the pre-stage driver output. A gate of the first NMOS transistor connects to a first node A, a gate of the second NMOS transistor connects to a third node C and a source region connects to a grounded node. The third node C also can receive the pre-stage driver output. There is a first resistor between the first node A and the system power source. There is a second PMOS transistor in between the first node A and the third node C and connect with two source/drain regions. And the substrate of the second PMOS transistor also connects with the first node A. Also, a gate of the second PMOS transistor connects with a second node B. There is a second resistor between the second node B and the system power source, and there is a capacitor between the second node B and the grounded node.
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings,
1. An electrostatic discharge protective circuit, protecting an internal circuit, comprising:
2. The ESD protective circuit of
3. The ESD protective circuit of
4. The ESD protective circuit of