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Electrostatic discharge protective circuit

Imported: 23 Feb '17 | Published: 22 Oct '02

Hung-Yi Chang, Yi-Hua Chang, Chih-Fu Chien

USPTO - Utility Patents

Abstract

An electrostatic discharge protective circuit can receive a pre-stage driver output and involve a first PMOS transistor, a first NMOS transistor and a second NMOS transistor and all connect in series. More particularly, a source region of the first PMOS transistor connects to a system power source; and a drain region connects to a conductive pad, and a gate receives the pre-stage driver output. A gate of the first NMOS transistor connects to a first node A, a gate of the second NMOS transistor connects to a third node C and a source region connects to a grounded node. The third node C also can receive the pre-stage driver output. There is a first resistor between the first node A and the system power source. There is a second PMOS transistor in between the first node A and the third node C and connect with two source/drain regions. And the substrate of the second PMOS transistor also connects with the first node A. Also, a gate of the second PMOS transistor connects with a second node B. There is a second resistor between the second node B and the system power source, and there is a capacitor between the second node B and the grounded node.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings,

FIG.

1 through FIG. 3 are illustrating three conventional design of the electrostatic discharge protective circuit;

FIG. 4 is illustrating an ESD circuit, it is for the output buffer to protect the prestage driver, according to one preferred embodiment of this invention;

FIG. 5 is illustrating an ESD circuit, it is for the input buffer to protect the internal circuit, according to one preferred embodiment of this invention;

FIG. 6 is illustrating an ESD circuit, it is similar to FIG. 4, and it is another electrostatic discharge protective charge and protects the pre-stage driver, according to one preferred embodiment of this invention; and

FIG. 7 is illustrating an ESD circuit, it is similar to the circuit in FIG. 5, and it is another electrostatic discharge protective charge and protects the internal circuit, according to one preferred embodiment of this invention.

Claims

1. An electrostatic discharge protective circuit, protecting an internal circuit, comprising:

2. The ESD protective circuit of claim 1, wherein the first resistor comprises a metal-oxide semiconductor resistor that builds by a third PMOS transistor, wherein a first source/drain region of the third PMOS transistor, a second source/drain region and a gate respectively connect to a system power source, the first node A and the grounded node.

3. The ESD protective circuit of claim 1, wherein the second resistor comprises a metal-oxide semiconductor resistor that builds by a fourth PMOS transistor, wherein a first source/drain region of the forth PMOS transistor, a second source/drain region and a gate respectively connect to a system power source, the second node B and the grounded node.

4. The ESD protective circuit of claim 1, connecting with a well control circuit, wherein the well control circuit connects to the conductive pad and a substrate of the first PMOS transistor.