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Dynamic sub-array group selection scheme

Imported: 24 Feb '17 | Published: 24 Aug '04

Bendik Kleveland, Roy E. Scheuerlein

USPTO - Utility Patents

Abstract

A method of selecting numbers of sub-array groups for simultaneous operation to optimize bandwidth biases a number of sub-array groups and compares a circuit state value, preferably voltage, to a reference parameter to determine if the operation can successfully be preformed for that number of sub-array groups. The comparison may be repeated with ifferent numbers of sub-array groups biased to find the optimum number of sub-array groups for the operation.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an illustration of a memory array divided into selectable sub-array groups.

FIG. 2 is a circuit diagram of a power supply and sub-array groups, and the sub-array group selector with its inputs and outputs.

FIG. 3 is an illustration of the input and output of a sub-array group selector.

FIG. 4 is a flow chart illustrating iterative selection of a number of groups of sub-arrays to read, write, or erase with the number of sub-array groups biased increased on each iteration.

FIG. 5 is a timing diagram illustrating signals during a bias and test of first one, then two sub-array groups.

FIG. 6 is flow chart illustrating iterative selection of a number of groups of sub-arrays to read, write, or erase with the number of sub-array groups biased decreased on each iteration.

FIG. 7 is a timing diagram illustrating signals during a bias and test of first two, then one sub-array groups.

FIG. 8 is a timing diagram illustrating signals when the circuit state value drops below the reference parameter before the operation is complete.

FIG. 9 is a flow chart illustrating the selection of the starting point for iteration based on environmental factors.

Claims

1. A method for dynamically selecting within a memory device a quantity of sections of a memory to be activated for a read/write/erase operation comprising the steps of:

2. The method of claim 1, further comprising:

3. The method of claim 2, wherein the number of sections biased in step (a) is increased for each repetition.

4. The method of claim 2, wherein the number of sections biased in step (a) is decreased for each repetition.

5. The method of claim 2, further comprising:

6. The method of claim 5, wherein the environmental value is an operating temperature.

7. The method of claim 5, wherein the environmental value is a user-selected setting.

8. The method of claim 2, wherein the number of sections biased in biasing step (a) is based on the quantity of sections read, written, or erased in a prior readlwrite/erase operation.

9. The method of claim 2, wherein the circuit state value is a voltage on the biased sections.

10. The method of claim 2, wherein the circuit state value is a current on the biased sections.

11. The method of claim 5, wherein the circuit state value is a voltage on the biased sections.

12. The method of claim 5, wherein the circuit state value is a current on the biased sections.

13. A memory device employing a method for dynamically selecting within the memory device a quantity of sections to be activated for a read/write/erase operation, said method comprising the steps of:

14. The device of claim 13, further comprising:

15. The device of claim 14, wherein the number of sections biased in step (a) is increased for each repetition.

16. The device of claim 14, wherein the number of sections biased in step (a) is decreased for each repetition.

17. The device of claim 14, further comprising:

18. The device of claim 17, wherein the environmental value is an operating temperature.

19. The device of claim 17, wherein the environmental value is a user-selected setting.

20. The device of claim 14, wherein the number of sections biased in biasing step (a) is based on the quantity of sections read, written, or erased in a prior read/write/erase operation.

21. The device of claim 14, wherein the circuit state value is a voltage on the biased sections.

22. The device of claim 14, wherein the circuit state value is a current on the biased sections.

23. The device of claim 17, wherein the curcuit state value is a voltage on the biased sections.

24. The device of claim 17, wherein the circuit state value is a current on the biased sections.