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Device comprising thermally stable, low dielectric constant material

Imported: 23 Feb '17 | Published: 22 Oct '02

Chorng-Ping Chang, Kin Ping Cheung, Chien-Shing Pai, Wei Zhu

USPTO - Utility Patents

Abstract

It has been discovered that for semiconductor devices such as MOSFETs, there is significant capacitive coupling in the front-end structure, i.e., the structure from and including the device substrate up to the first metal interconnect level. The invention therefore provides a device comprising a silicon substrate, an isolation structure in the substrate (e.g., shallow trench isolation), an active device structure (e.g., a transistor structure), a dielectric layer over the active device structure, and a metal interconnect layer over the dielectric layer (metal-1 level). At least one of the dielectric components of the front-end structure comprise a material exhibiting a dielectric constant less than 3.5. This relatively low dielectric constant material reduces capacitive coupling in the front-end structure, thereby providing improved properties in the device.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a typical MOSFET device structure.

FIG. 2 illustrates the capacitive coupling exhibited by a MOSFET structure such as illustrated in FIG.

1.

FIG. 3 illustrates the device structure used for a simulation experiment involving variation in dielectric constant values.

FIG. 4 illustrates the effect of providing low material in the front-end structure.

Claims

1. A device comprising:

2. The device of claim 1, wherein the substrate is selected from silicon, gallium arsenide, and silicon-on-insulator.

3. The device of claim 1, wherein the active device structure comprises a gate conductor, a gate dielectric, and a gate junction.

4. The device of claim 1, wherein the material exhibits a dielectric constant less than 3.0.

5. The device of claim 1, wherein the material exhibits 10 to 60 vol.% porosity.

6. The device of claim 1, wherein the material is selected from ceramics, thermosettings polymers, and carbon materials.

7. The device of claim 6, wherein the material is silica.

8. The device of claim 1, wherein the material exhibits an average pore size less than 25 nm.

9. A device comprising:

10. A device comprising:

11. A device comprising a metal-oxide-silicon field effect transistor that comprises a front-end structure comprising a nanoporous silica that exhibits a dielectric constant less than 3.5.

12. The device of claim 11, wherein the dielectric material exhibits a dielectric constant less than 3.0.

13. The device of claim 11, wherein the nanoporous silica exhibits an average pore size less than 25 nm.

14. A device comprising:

15. The device of claim 14, wherein the substrate is selected from silicon, gallium arsenide, and silicon-on-insulator.

16. The device of claim 14, wherein the material exhibits a dielectric constant less than 3.0.

17. The device of claim 14, wherein the material comprises a nanoporous silica.

18. A device comprising:

19. The device of claim 18, wherein the dielectric layer comprises a material exhibiting a dielectric constant less than 3.5.