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Design of a parallel low power flash A/D converter for the sub-sampling IR-UWB receiver

Research paper by Shenjie Wang, Catherine Dehollain, Zhiliang Hong

Indexed on: 25 Sep '12Published on: 25 Sep '12Published in: Analog Integrated Circuits and Signal Processing



Abstract

This paper presents the design of a dual-channel 4-bit analog-to-digital converter (ADC) for the sub-sampling impulse radio ultra-wideband receiver with the sampling rate of 2.112 GS/s. The ADC’s specifications are optimized at the system level. Two parallel channels help to achieve high conversion speed and low power consumption. To tackle the problem of clock mismatch between the channels, a twice sampling front end is used. An improved averaging termination technique using intended asymmetric spatial filter response is proposed. This circuit is designed in a 0.13 μm CMOS technology with 1.2 V power supply. Simulation results show a 26 dB SNDR at 2.112 GHz sampling rate with 36 mW power consumption and the effective figure of merit value is 0.24 pJ/step.