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Delay circuit and semiconductor integrated circuit having same

Imported: 24 Feb '17 | Published: 09 Apr '02

Hiroyoshi Tomita

USPTO - Utility Patents

Abstract

A delay circuit including a plurality of interpolators connected in cascade. Each of the interpolators receives a reference clock signal and a clock signal output from the preceding interpolator. One of the interpolators generates a clock signal whose transition edge is between the transition edge of the reference clock signal and the transition edge of the clock signal. The subsequent interpolators operate as delay stages, thereby generating a delayed clock signal delaying from the reference clock signal by a predetermined time. It is possible to make smaller the minimum unit of a delay adjustment to the delayed clock signal by using the interpolators. A semiconductor integrated circuit including the delay circuit supplies ratio information to the phase adjustment circuits based on the result of comparing the phase of the reference clock signal with the phase of the delayed clock signal from a phase comparator and makes the phase of the delayed clock signal coincide with the phase of the reference clock signal. As a result, the phase adjustment can be made with reliability even when a reference clock signal of higher frequency is supplied.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The nature, principle, and utility of the invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings in which like parts are designated by identical reference numbers, in which:

FIG. 1 is a block diagram showing the conventional semiconductor integrated circuit;

FIG. 2 is a flowchart showing the control for the conventional phase adjustment to a clock signal;

FIG. 3 is a timing chart showing the essential signals in the phase adjustment in FIG. 2;

FIG. 4 is a block diagram showing the basic principle of first through third embodiments;

FIG. 5 is a block diagram showing the basic principle of a fourth embodiment;

FIG. 6 is a block diagram showing the clock control unit in the first embodiment;

FIG. 7 is a block diagram showing the delayed clock generator in FIG. 6;

FIG. 8 is a circuit diagram showing an interpolator in FIG. 7;

FIG. 9 is a circuit diagram showing a switch part in FIG. 7;

FIG. 10 is a circuit diagram showing the shift register in FIG. 7;

FIG. 11 is a timing chart showing the input waveforms and the output waveforms of the interpolators;

FIG. 12 is a block diagram showing the phase comparison unit in FIG. 5;

FIG. 13 is a block diagram showing the first divider and the second divider in FIG. 12;

FIG. 14 is a circuit diagram showing a frequency divider in FIG. 13;

FIG. 15 is a timing chart showing the basic operations of the frequency divider in FIG. 14;

FIG. 16 is a timing chart showing the basic operations of the frequency divider in FIG. 14;

FIG. 17 is a circuit diagram showing the phase comparator in FIG. 12;

FIG. 18 is a circuit diagram showing the rough/fine control unit in FIG. 6;

FIG. 19 is a controlling state diagram showing the operations of the combinational circuit in FIG. 18;

FIG. 20 is a block diagram showing the rough control circuit in FIG. 6;

FIG. 21 is a circuit diagram showing the rough controller in FIG. 20;

FIG. 22 is a controlling state diagram showing the operations of the combinational circuit in FIG. 21;

FIG. 23 is a timing chart showing an overview of the operations of the rough controller in FIG. 20;

FIG. 24 is a circuit diagram showing the rough shift latch in FIG. 20;

FIG. 25 is a circuit diagram showing the shift direction latch in FIG. 20;

FIG. 26 is a block diagram showing the fine control unit in FIG. 6;

FIG. 27 is a circuit diagram showing the fine controller in FIG. 26;

FIG. 28 is a controlling state diagram showing the operations of the fine controller in FIG. 27;

FIG. 29 is a flowchart showing the control for the phase adjustment in the first embodiment;

FIG. 30 is a flowchart showing the control for the initial setup and the rough initial adjustment of the phase adjustment in the first embodiment;

FIG. 31 is a flowchart showing the control for the fine initial adjustment in the first embodiment;

FIG. 32 is a flowchart showing the control for the fine initial adjustment in the first embodiment;

FIG. 33 is a flowchart showing the control for the rough/fine adjustment in the first embodiment;

FIG. 34 is a flowchart showing the control for the rough/fine adjustment in the first embodiment;

FIG. 35 is a timing chart showing the operation of the start signal generator in FIG. 6;

FIG. 36 is a timing chart showing the states of the respective clock signals in the phase comparison unit in FIG. 12;

FIG. 37 is an explanatory diagram showing the states of the interpolators after the initial setup in the first embodiment;

FIG. 38 is an explanatory diagram showing an overview of the switch control to the interpolators at the rough initial adjustment in the first embodiment;

FIG. 39 is an explanatory diagram showing the internal clock signal's variations resulting from the initial values of the binary counter at the rough initial adjustment in the first embodiment;

FIG. 40 is an explanatory diagram showing an overview of the fine initial adjustment in the first embodiment;

FIG. 41 is a block diagram showing the clock control unit in the second embodiment;

FIG. 42 is a block diagram showing the phase comparison unit in FIG. 41;

FIG. 43 is a circuit diagram showing the fine phase comparator in FIG. 42;

FIG. 44 is a circuit diagram showing the rough phase comparator in FIG. 42;

FIG. 45 is a timing chart showing the operations of the rough phase comparator in the second embodiment;

FIG. 46 is a circuit diagram showing the rough/fine control unit in FIG. 41;

FIG. 47 is a circuit diagram showing the rough control unit in FIG. 41;

FIG. 48 is a circuit diagram showing the rough controller in FIG. 47;

FIG. 49 is a controlling state diagram showing the operations of the combinational circuit in FIG. 48;

FIG. 50 is a flowchart showing the control for the phase adjustment in the second embodiment;

FIG. 51 is a block diagram showing the first divider in the third embodiment;

FIG. 52 is a timing chart showing the operations of the first and second dividers at the beginning of the phase adjustment in the third embodiment;

FIG. 53 is a block diagram showing the clock control unit in the fourth embodiment;

FIG. 54 is a block diagram showing the delay control circuit in FIG. 53;

FIG. 55 is a block diagram showing the initializing circuit in FIG. 53;

FIG. 56 is a circuit diagram showing an interpolator in FIGS. 54 and 55;

FIG. 57 is a circuit diagram showing the fine counter in FIG. 53;

FIG. 58 is a timing chart showing the operation of the fine counter in FIG. 57;

FIG. 59 is a circuit diagram showing a flip-flop in FIG. 57;

FIG. 60 is a timing chart showing the operation of the flip-flop in FIG. 57;

FIG. 61 is a block diagram showing the D/A converter in FIG. 53;

FIG. 62 is a circuit diagram showing a D/A converter in FIG. 61;

FIG. 63 is a timing chart showing the operation of the D/A converter in FIG. 62;

FIG. 64 is an explanatory diagram showing the relationship between the output voltage of the D/A converter in FIG.

62 and the delay time of an interpolator;

FIG. 65 is a circuit diagram showing the second selector in FIG. 53;

FIG. 66 is a circuit diagram showing the switching circuit and the first selector in FIG. 53;

FIG. 67 is an explanatory diagram showing an overview of the operations of the switching circuit and the first selector in FIG. 53;

FIG. 68 is an explanatory diagram showing the states of the interpolators in FIG. 54;

FIG. 69 is another explanatory diagram showing the states of the interpolators in FIG. 54;

FIG. 70 is a flowchart showing the control for the phase adjustment in the fourth embodiment;

FIG. 71 is an explanatory diagram showing an example of the phase adjustment in the fourth embodiment;

FIG. 72 is a circuit diagram showing another example of the interpolator;

FIG. 73 is a circuit diagram showing another example of the interpolator and the buffer; and

FIG. 74 is a circuit diagram showing another example of the interpolator and the buffer.

Claims

1. A delay circuit comprising a plurality of interpolators connected in cascade, the interpolators each receiving a clock signal from the preceding interpolator and a reference clock signal, wherein:

2. The delay circuit according to claim 1, wherein a predetermined number of interpolators prior to said phase adjustment circuit stop(s) operating.

3. The delay circuit according to claim 2, wherein a delay time of said delayed clock signal is adjusted in two steps; selecting one of said interpolators that operates as said phase adjustment circuit and phase controlling said adjustment clock signal in said phase adjustment circuit.

4. A semiconductor integrated circuit comprising a delay circuit, wherein:

5. The semiconductor integrated circuit according to claim 4, further comprising:

6. The semiconductor integrated circuit according to claim 5, wherein said ratio information is generated by a shift register.

7. The semiconductor integrated circuit according to claim 5, wherein said ratio information is generated by a counter.

8. The semiconductor integrated circuit according to claim 5, wherein:

9. The semiconductor integrated circuit according to claim 8, wherein said control circuit judges said comparison result to be equal to or shorter than said delay time of said delay stage when said phase of said reference clock signal and said phase of said delayed clock signal are reversed.

10. The semiconductor integrated circuit according to claim 5, wherein said interpolators are respectively connected to independent power supply lines.

11. The semiconductor integrated circuit according to claim 5, further comprising a start signal generator for activating a start signal in synchronization with said reference clock signal at the beginning of a phase comparison.

12. The semiconductor integrated circuit according to claim 11, wherein said start signal generator activates said start signal in synchronization with the falling edge of said reference clock signal.

13. The semiconductor integrated circuit according to claim 5, further comprising frequency dividers for respectively dividing frequencies of said reference clock signal and said delayed clock signal to produce a divided reference clock signal and a divided delayed clock signal, and wherein

14. The semiconductor integrated circuit according to claim 13, further comprising a start signal generator for activating a start signal in synchronization with said reference clock signal at the beginning of a phase comparison, and wherein

15. The semiconductor integrated circuit according to claim 14, wherein said predetermined number of clocks can be set in accordance with a frequency of said reference clock signal.

16. The semiconductor integrated circuit according to claim 14, further comprising a mode register for setting said predetermined number of clocks.

17. The semiconductor integrated circuit according to claim 14, further comprising a fuse for setting said predetermined number of clocks.

18. The semiconductor integrated circuit according to claim 14, further comprising a control terminal for setting said predetermined number of clocks.

19. The semiconductor integrated circuit comprising a main delay circuit having a delay circuit, a sub delay circuit, a selecting circuit, a phase comparator, and a control circuit, and wherein:

20. The semiconductor integrated circuit according to claim 19, wherein said sub delay circuit sets a delay time equal to or longer than a delay time which one of said interpolators in said main delay circuit can set.

21. The semiconductor integrated circuit according to claim 19, wherein said main delay circuit sets a delay time equal to or longer than one cycle of said reference clock signal.

22. The semiconductor integrated circuit according to claim 19, wherein said interpolators are respectively connected to independent power supply lines.

23. The semiconductor integrated circuit according to claim 19, further comprising frequency dividers for respectively dividing frequencies of said reference clock signal and said internal clock signal to produce a delayed reference clock signal and a delayed internal clock signal, and wherein

24. The semiconductor integrated circuit according to claim 23, further comprising a start signal generator for activating a start signal in synchronization with said reference clock signal at the beginning of a phase comparison, and wherein

25. The semiconductor integrated circuit according to claim 24, wherein said predetermined number of clocks can be set in accordance with the frequency of said reference clock signal.

26. The semiconductor integrated circuit according to claim 24, further comprising a mode register for setting said predetermined number of clocks.

27. The semiconductor integrated circuit according to claim 24, further comprising a fuse for setting said predetermined number of clocks.

28. The semiconductor integrated circuit according to claim

24, further comprising a control terminal for setting said predetermined number of clocks.

29. The semiconductor integrated circuit according to claim 19, further comprising:

30. The semiconductor integrated circuit according to claim 29, wherein:

31. The semiconductor integrated circuit according to claim 29, wherein said third interpolators in said adjustment delay circuit, said interpolators in said main delay circuit, and said second interpolators in said sub delay circuit are identical with one another.

32. The semiconductor integrated circuit according to claim 31, wherein the number of said interpolators in said main delay circuit is more than the number of said interpolators in said adjustment delay circuit.

33. The semiconductor integrated circuit according to claim 29, wherein a delay time which said main delay circuit can set is equal to or longer than a delay time which said adjustment delay circuit can set.

34. The semiconductor integrated circuit according to claim 29, wherein control for said coinciding by said control circuit is performed after said adjustment circuit adjusting said maximum delay time.

35. The semiconductor integrated circuit according to claim 34, wherein:

36. The semiconductor integrated circuit according to claim 35, wherein said control circuit judges said phase difference to be equal to or shorter than said maximum delay time when said phase of said reference clock signal and said phase of said delayed clock signal are reversed.

37. The semiconductor integrated circuit according to claim 35, wherein said rough adjustment is performed with said ratio information set at a central value.