Current sense amplifier circuit

A current sense amplifier circuit is provided with a reference current generator for generating a reference current according to the characteristics of a memory cell, and a current comparator, and the current comparator compares the memory cell current with the reference current. Thereby, the range of the operating power supply voltage is increased. Further, a current sense amplifier circuit is provided with plural sets of reference current generators and current comparators, and the reference current generators generate reference currents of different amounts corresponding to plural states the memory cell can take, and the current comparators compare the respective reference currents with the memory cell current. Therefore, it is possible to detect the current in the memory cell that is set in multiple states.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram illustrating a current sense amplifier circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating the construction of a reference current generator included in the current sense amplifier circuit according to the first embodiment.

FIG. 3 is a circuit diagram illustrating a current sense amplifier circuit according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram illustrating a current sense amplifier circuit according to a third embodiment of the present invention.

FIG. 5 is a circuit diagram illustrating a current sense amplifier circuit according to a fourth embodiment of the present invention.

FIG. 6 is a circuit diagram illustrating a current sense amplifier circuit according to a fifth embodiment of the present invention.

FIG. 7 is a circuit diagram illustrating a conventional current sense amplifier circuit.

1. A current sense amplifier circuit connected to a data line to which a bit line of a memory cell array is connected through a selection transistor, comprising:

2. A current sense amplifier circuit as defined in claim 1, wherein the reference current generator comprises:

3. A current sense amplifier circuit as defined in claim 2, wherein the fifth N type MOS transistor is a memory cell.

4. A current sense amplifier circuit as defined in claim 1, wherein the reference current generator comprises:

5. A current sense amplifier circuit as defined in claim 1, wherein the reference current generator comprises:

6. A current sense amplifier circuit connected to a data line to which a bit line of a memory cell array is connected through a selection transistor, comprising:

7. A current sense amplifier circuit as defined in claim 6 further comprising a data conversion unit which receives read data having n+1 states indicated by the output values from the output terminals of the n pieces of current comparators, and associates the respective read data with gray codes according to the magnitudes of the detected currents of the data line, and outputs the data associated with the gray codes.

8. A current sense amplifier circuit as defined in claim 7 wherein:

9. A current sense amplifier circuit as defined in claim 6, wherein the reference current generator comprises:

10. A current sense amplifier circuit as defined in claim 9, wherein the fifth N type MOS transistor is a memory cell.

11. A current sense amplifier circuit as defined in claim 6, wherein the reference current generator comprises:

12. A current sense amplifier circuit as defined in claim 6, wherein the reference current generator comprises: