Imported: 24 Feb '17 | Published: 16 Mar '04

USPTO - Utility Patents

A clock generating circuit and method thereof is provided. The frequency ratio between the output clock and the system clock is calculated as that the first preset value divides by the second preset value. A data value is stored into a register. The sum of the data value and the first preset value is calculated as a first result by the first adder. The sum of the first result and the second preset value is calculated as a second result by the second adder. A multiplexer (MUX) is used to select the data value that should be stored into the register at next system clock from the first result and the second result according to the level of the output clock. The first result is compared with a reference value by the first comparator to generate the output clock, so that the frequency of the output clock can be changed arbitrarily and it is not required to redesign the circuit.

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention, and together with the description, serve to explain the principles of the invention. In the drawings,

1. A clock generating circuit, suitable for generating a first output clock from a system clock, wherein a frequency ratio between the first output clock and the system clock is a value of a first preset value divided by a second preset value, and the clock generating circuit comprises:

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13. A clock generating method, suitable for generating a first output clock from a system clock, wherein the frequency ratio between the first output clock and the system clock is a value of the first preset value divided by the second preset value, and the clock generating method comprises the steps of:

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