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Booster circuit

Imported: 23 Feb '17 | Published: 22 Oct '02

Fumiaki Miyamitsu

USPTO - Utility Patents

Abstract

The objective of the invention is to provide a booster circuit with reduced power consumption and switching noise. Booster circuit

1 of the present invention has gate circuits

4

1

-4

7 an auxiliary control circuit

9. Each of gate circuits

4

1

-4

7 has charging/discharging circuit

11 and auxiliary charging/discharging circuit

12 used for charging/discharging capacitors

5

1

-5

7. Under the control of auxiliary control circuit

9, said charging/discharging circuit

11 can operate independently or operate together with auxiliary charging/discharging circuit

12. When the booster circuit is started, charging/discharging circuit

11 and auxiliary charging/discharging circuit

12 are operated together to increase the drivability of gate circuits

4. As a result, the charging time of capacitors

5

1

-5

7 in charge-pump circuits

2

2

-2

7 can be shortened. On the other hand, at steady state, charging/discharging circuit

11 operates independently. As a result, the drivability of the gate circuits is reduced compared with that at the time when the booster circuit is started. Consequently, the loss in power consumption and noise can be reduced.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram illustrating the booster circuit disclosed in an embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating the relationship between the gate circuits and the auxiliary control circuit of the booster circuit disclosed in an embodiment of the present invention.

FIG. 3 is a diagram illustrating the waveform of the output voltage of each charge-pump circuit when the booster circuit of the present invention is started.

FIG. 4 is a diagram illustrating the steady-state output voltage waveform of each charge-pump circuit of the booster circuit disclosed in the present invention.

FIG.

5(

a) is a diagram illustrating the waveform of the current flowing in a gate circuit with a high drivability.

FIG.

5(

b) is a diagram illustrating the waveform of the current flowing in a gate circuit with a low drivability.

FIG. 6 is a circuit diagram illustrating the booster circuit disclosed in another embodiment of the present invention.

FIG. 7 is a waveform diagram explaining the operation of the ring oscillator in the booster circuit disclosed in another embodiment of the present invention.

FIG. 8 is a diagram explaining a variant of the booster circuit disclosed in another embodiment of the present invention.

FIG. 9 is a circuit diagram illustrating the booster circuit disclosed in yet another embodiment of the present invention.

FIG. 10 is a circuit diagram illustrating an example of the conventional booster circuit.

FIG. 11 is a waveform diagram explaining the operation of the conventional booster circuit.

Claims

1. A voltage booster circuit comprising:

2. The booster circuit of claim 1 wherein the first and second charge/discharge circuits are identical.

3. The booster circuit of claim 1 wherein the disable circuit couples base drive signals of the second charge/discharge circuits to ground.

4. The booster circuit of claim 2 wherein the disable circuit couples base drive signals of the second charge/discharge circuits to ground.

5. The booster circuit of claim 1 wherein the output voltage monitoring circuit generates the third control signal to disable the second charge/discharge circuits when a steady state output voltage is reached.

6. The booster circuit of claim 5 wherein the output voltage monitoring circuit does not respond to changes in output voltage due to load current.

7. The booster circuit of claim 2 wherein the output voltage monitoring circuit generates the third control signal to disable the second charge/discharge circuits when a steady state output voltage is reached.

8. The booster circuit of claim 2 wherein the output voltage monitoring circuit does not respond to changes in output voltage due to load current.

9. The booster circuit of claim 2 wherein the output voltage monitoring circuit generates the third control signal to disable the second charge/discharge circuits when a steady state output voltage is reached.

10. The booster circuit of claim 3 wherein the output voltage monitoring circuit does not respond to changes in output voltage due to load current.

11. The booster circuit of claim 1 wherein a first stage of the plurality of stages has the one terminal of the rectifying element connected to a voltage supply.

12. The booster circuit of claim 1 wherein a last stage of the plurality of stages has the output of the stage connected to the output of the booster circuit via a rectifying element.

13. The booster circuit of claim 11 wherein a last stage of the plurality of stages has the output of the stage connected to the output of the booster circuit via a rectifying element.

14. The booster circuit of claim 2 wherein a first stage of the plurality of stages has the one terminal of the rectifying element connected to a voltage supply.

15. The booster circuit of claim 2 wherein a last stage of the plurality of stages has the output of the stage connected to the output of the booster circuit via a rectifying element.

16. The booster circuit of claim 3 wherein a first stage of the plurality of stages has the one terminal of the rectifying element connected to a voltage supply.

17. The booster circuit of claim 3 wherein a last stage of the plurality of stages has the output of the stage connected to the output of the booster circuit via a rectifying element.

18. A voltage booster circuit comprising a plurality of booster stages, each stage comprising a rectifying element, a capacitor and a drive circuit, wherein the drive circuit comprises: