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Apparatus and method for odd integer signal division

Imported: 23 Feb '17 | Published: 22 Oct '02

Michael Carson, Dat Nguyen

USPTO - Utility Patents

Abstract

The present invention provides a method and/or circuit for achieving a near 50 percent duty cycle divide-by-odd-integer output of an input reference clock.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a circuit embodiment of an earlier divide-by-3 circuit.

FIG. 2 shows a circuit embodiment of a divide-by-7 circuit according to particular embodiments of the invention.

FIG. 3 is an example timing diagram of the circuit shown in FIG.

2.

FIG. 4 shows a generalized circuit diagram for an expandable odd integer division circuit.

FIG. 5 shows a further example divide-by-5 circuit according to particular embodiments of the invention.

FIG. 6 shows an information processing device that can embody aspects of the present invention.

Claims

1. A circuit for performing odd integer division with a near 50 percent duty cycle comprising:

2. The device according to claim 1 wherein said outputs comprise:

3. The device according to claim 1 wherein said outputs comprise:

4. The device according to claim 1 wherein said feedback is inverted.

5. The device according to claim 1 wherein said function is an XOR function.

6. The device according to claim 1 wherein said clock input that is inverted is provided to a middle delay element.

7. The device according to claim 1 further comprising a reset input providing common reset of each of said delay elements.

8. A method of providing odd integer signal divisions with an odd integer divisor of five or greater using a chain of delay stages comprising:

9. The method according to claim 8 wherein N is selected to be equal to integer result of one-half of the desired divide-by integer.

10. The method according to claim 8 wherein said feedback is inverted.

11. The method according to claim 8 further comprising:

12. A circuit for performing odd integer division with a near 50 percent duty cycle comprising:

13. The device according to claim 12 further comprising:

14. The device according to claim 12 further comprising:

15. The device according to claim 12 wherein an output of said combiner is a divide-by-five periodic signal of an input reference signal applied to said first path.

16. A circuit for performing odd integer division with a near 50 percent duty cycle comprising:

17. The device according to claim 16 further wherein:

18. A circuit for performing odd integer division with a near 50 percent duty cycle comprising:

19. The device according to claim 12 wherein said combiner provides an XOR function.

20. An electronic data file, recorded or transmitted on a digital medium, that when loaded into an appropriately configured digital apparatus causes the apparatus to operate is in accordance with the method of claim 8.

21. An electronic data file, recorded or transmitted on a digital medium, that when loaded into an appropriately configured digital apparatus causes the apparatus to embody the system of claim 1.

22. The device according to claim 12 wherein the third group is clocked with an inverted clock signal so that the third group has a clock offset from other stages.