# Apparatus and method for constant delta current control in a capacitor charger

Imported: 13 Feb '17 | Published: 30 Jan '07

Chung-Lung Pai, Kwan-Jen Chu, Chun-Yen Huang, Jing-Meng Liu

USPTO - Utility Patents

## Abstract

In a capacitor charger, a transformer has a primary winding connected between an input voltage and a switch for generating a primary current flowing through the primary winding by switching the switch to thereby induce a secondary current flowing through a secondary winding of the transformer and a secondary voltage tapered from the secondary winding, a control apparatus and method adjusts the on-time period for the switch in response to the input voltage. The charging time and charging current are independent of the input voltage, and there is no power loss resulted from current sense to the primary current.

## Description

### FIELD OF THE INVENTION

The present invention is related generally to a capacitor charger, and more particularly, to an apparatus and method for constant delta current control in a capacitor charger. As generally used in the art, the term “delta current” is referred hereinafter to the difference between the maximum and minimum in the desired range of a current.

### BACKGROUND OF THE INVENTION

Portable apparatus is more and more popular, and therefore capacitor charger it uses receives more attentions than ever. FIG. 1 shows a diagram of a conventional capacitor charger 100 implemented with ring choke converter (RCC) circuit, in which a transformer T1 connected with an input voltage Vin transforms a primary current IP to a secondary current IS that flows through a diode D1 to charge a capacitor C1 to generate an output voltage Vout at the output 112 of the charger 100 to supply for a load RL. To control the current IP or IS, a power transistor Q1 has its collector 104 and emitter 108 connected to the primary winding N1 of the transformer T1 and ground, respectively, and resistors R1 and R2 are connected between the input 102 of the charger 100 and another primary winding N3 of the transformer T1 for the bias to the base of the transistor Q1. Although the capacitor charger 100 is cheaper, the transformer T1 has a more complicated structure to construct the circuit, and the power transistor Q1 causes higher switching loss. In addition, there are too many parameters effective to the current IP, for example the input voltage Vin, transformer T1 and power transistor Q1, for the current IP to be precisely controlled. Furthermore, the maximum of the current IP has to be set much smaller than the base current Ib of the power transistor Q1, and much longer charging time is thus needed.

FIG. 2 shows a diagram of another conventional capacitor charger 200, in which a transformer T1 connected with a battery voltage Vbat transforms a primary current IP to a secondary current IS to charge a capacitor C4 for generating an output voltage Vout. To control the current IP or IS, a current sense resistor RS1 is connected between a transistor Q1 and ground, another current sense resistor RS2 is connected between the secondary winding N2 of the transformer T1 and ground, and operational amplifiers A1 and A2 are used to amplify the voltage drops across the resistors R1 and R2 to generate detector signals S1 and S2 for the inputs R and S of a flip-flop 206, respectively, so as to generate a switch signal S3 for switching the transistor Q1 through a driver 208. In the capacitor charger 200, the primary current IP and secondary current IS of the transformer T1 are directly detected by the current sense resistors RS1 and RS2 to determine the maximum and minimum of the primary current IP. However, for not affecting the operations of the charger 200, only much small resistors can be used for the current sense resistors RS1 and RS2, and therefore the voltage drops across the resistors RS1 and RS2 are very small. As a result, the currents flowing through the resistors RS1 and RS2 cannot be precisely detected, and it is also easily to introduce spikes on the primary current IP out of the maximum current that the battery could supply for the charger 200. Furthermore, the charging current IP of the charger 200 is not easy to set.

FIG. 3 shows an application of yet another conventional capacitor charger 300 for a flash lamp module 306, in which a transformer 304 has a primary winding L1 connected between an input voltage Vbat and a transistor 308 to transform the primary current IP to a secondary current IS by switching the transistor 308, so as to charge a capacitor C1 for supplying to the flash lamp module 306. To control the charging current IS, resistors R1, R2 and R3 are connected in series between the output 316 of the charger 300 and ground to detect the voltage on the capacitor C1 by voltage dividing to provide a feedback signal VFB to a controller integrated circuit chip 302, so as to stop charging the capacitor C1 when the voltage on the capacitor C1 reaches its threshold. In the capacitor charger 300, it is the maximum duty of the transistor 308 to be used to determine the charging current IP, and unfortunately, which is easy to have the transformer T1 to be magnetically saturated and inefficiently operated. Moreover, the input voltage Vbat is supplied by battery, and it will decade as time goes by, resulting in longer and longer charging time for the capacitor C1 to reach the same voltage.

### SUMMARY OF THE INVENTION

One object of the present invention is to provide a control apparatus and method for a capacitor charger.

Another object of the present invention is to provide an apparatus and method for a capacitor charger without introducing power loss resulted from current detection.

Yet another object of the present invention is to provide an apparatus and method for a capacitor charger without having the transformer to be magnetically saturated.

In a capacitor charger using a transformer to transform a primary current to a secondary current to charge a capacitor and a switch connected in series with the primary winding of the transformer to switch the primary current, according to the present invention, a control apparatus and method are used to adjust the on-time period of the switch depending on the input voltage connected to the capacitor charger. Preferably, the control apparatus includes a voltage generator to provide a voltage varying with the input voltage for the control apparatus to determine the on-time period for the switch. Preferably, the voltage provided by the voltage generator is supplied to a current source to generate a reference current that is mirrored by a current mirror to a charge/discharge circuit to generate a charged voltage for a comparator to compare with a reference voltage to generate a comparison signal, and on-time control logics is preferably included in the control apparatus to determine the on-time period of the switch in response to the comparison signal.

From one aspect of the present invention, it is easy to determine and set the delta current flowing through the primary or secondary winding of the transformer, thereby achieving simple and precise control.

From another aspect of the present invention, the delta current of the primary winding of the transformer is independent of the input voltage connected to the primary winding, thereby preventing the transformer from magnetic saturation.

From still another aspect of the present invention, there are no current sense resistors connected in series to the current path of the primary or secondary winding of the transformer, thereby introducing no power loss resulted therefrom.

According to the present invention, the on-time period of the switch varies with the input voltage, and therefore the influence to the delta current of the primary current resulted from the variation of the input voltage is eliminated, resulting in the delta current of the charging current could be a constant value and easily to set. In addition, the secondary current could be precisely controlled due to the off-time control, and therefore, the maximum of the primary current and the minimum of the secondary current both could be controlled in a desired range, thereby no magnetic saturation occurred to the transformer. Moreover, no current sense to the primary winding of the transformer is used to determine the on-time period of the switch, and thus there will be no power loss resulted from current detection to be introduced.

### DETAILED DESCRIPTION OF THE INVENTION

FIG. 4 shows an application of one embodiment according to the present invention for a flash lamp module. In a capacitor charger 400, a transformer 416 has a primary winding L1 and a secondary winding L2 with a turns ratio NP:NS, a transistor M1 is connected between the primary winding L1 and ground GND, and the primary current IP flowing through the primary winding L1 is controlled by the switching transistor M1. Briefly, the capacitor charger 400 has system control logics 414 to switch the transistor M1 through a driver 424 in response to an on-time decision circuit and an off-time decision circuit. The on-time decision circuit includes on-time control logics 412 to determine the on-time period Ton for the transistor M1 according to the output SC generated by an on-time period generator that includes a voltage generator 402, a current source 404, a current mirror 406, a charge/discharge circuit 408, and a comparator 410. On the other hand, the off-time decision circuit includes off-time control logics 420 to determine the off-time period Toff for the transistor M1 according to the output SS generated by an off-time period generator 418. Systematically, neither the charging time nor the charging current is dependent of the battery voltage Vbat.

In the on-time period generator, the voltage generator 402 is connected with the input voltage Vbat to generate a voltage Vd varying with the input voltage Vbat. In this embodiment, as shown in FIG. 4, the voltage generator 402 includes a voltage divider composed of resistors R1 and R2 connected in series, and therefore provides the voltage

$V d = V bat × R 2 R 1 + R 2 . [ EQ ⁢ - ⁢ 1 ]$
The current source 404 determines a current IA according to the voltage Vd. In this embodiment, the current source 404 includes a voltage-to-current converter that has a transconductive amplifier comprised of an operational amplifier 4042 and a transistor 4044 and a resistor R3 connected between the transistor 4044 and ground GND, in which the operational amplifier 4042 has a non-inverting input connected with the voltage Vd, an inverting input connected to the resistor R3, and an output connected to the gate of the transistor 4044. Due to the virtual ground between the inputs of the operational amplifier 4042, the voltage drop across the resistor R3 is also Vd, and thus determines the current

$I A = V d R 3 . [ EQ ⁢ - ⁢ 2 ]$
From the equations EQ-1 and EQ-2,it is obtained the current

$I A = V bat × R 2 R 1 + R 2 × 1 R 3 . [ EQ ⁢ - ⁢ 3 ]$
The current IA provided by the current source 404 is used as the reference current for the current mirror 406 to generate a mirror current IB by mirroring the reference current IA supplied to the charge/discharge circuit 408. Since the reference current IA and the mirror current IB have the same magnitude, they are

$I B = I A = V bat × R 2 R 1 + R 2 × 1 R 3 . [ EQ ⁢ - ⁢ 4 ]$
The charge/discharge circuit 408 includes a capacitor C1 and a transistor M2 serving as a switch shunt to the capacitor C1. The current IB charges the capacitor C1 to generate a charged voltage VC that is compared with a reference voltage Vtf by the comparator 410 to generate the comparison signal SC for the on-time control logics 412 to determine the on-time period

$T on = C 1 × V tf I B . [ EQ ⁢ - ⁢ 5 ]$
From the equations EQ-4 and EQ-5, it is obtained the on-time period

$T on = C 1 × V tf × R 3 × ( R 1 + R 2 ) V bat × R 2 . [ EQ ⁢ - ⁢ 6 ]$

In the off-time decision circuit, the off-time period generator 418 generates the signal SS according to the secondary current IS, and thus the off-time control logics 420 could determine the off-time period Toff supplied to the system control logics 414. Based on the on-time period Ton and the off-time period Toff, the system control logics 414 could switch the transistor M1 by the driver 424 to control the primary current IP, and moreover, reset the capacitor C1 by turning on the transistor M2 shunt to the capacitor C1 in the charge/discharge circuit 408.

The transformer 416 has the primary current
IP=Vbat×Ton=L1×ΔIP,  [EQ-7]
where ΔIP is the delta current, i.e., the difference between the maximum and minimum, of the primary current IP. It thus has the on-time period

$T on = L 1 × Δ ⁢ ⁢ I P V bat . [ EQ ⁢ - ⁢ 8 ]$
From the equations EQ-6 and EQ-8, it is obtained the on-time period

$T on = L 1 × Δ ⁢ ⁢ I P V bat = C 1 × V tf × R 3 × ( R 1 + R 2 ) V bat × R 2 , [ EQ ⁢ - ⁢ 9 ]$
and thereby the delta current

$Δ ⁢ ⁢ I P = C 1 × V tf × R 3 × ( R 1 + R 2 ) L 1 × R 2 . [ EQ ⁢ - ⁢ 10 ]$
From the equation EQ-10, it is shown that the delta current ΔIP of the primary current IP in the transformer 416 is independent of the input voltage Vbat, and is determined by the device parameters R1, R2, R3, C1, Vtf, and L1.

Since the maximum IPmax and minimum IPmin of the primary current IP follow the relation
IPmax=ΔIP+IPmin,  [EQ-11]
and the transformer 416 has the transformation

$I P ⁢ min = N S N P × I S ⁢ min , [ EQ ⁢ - ⁢ 12 ]$
where ISmin is the minimum of the secondary current IS, it is obtained the maximum of the primary current

$I P ⁢ ⁢ max = Δ ⁢ ⁢ I P + N S N P × I S ⁢ ⁢ min . [ EQ ⁢ - ⁢ 13 ]$
If the minimum ISmin of the secondary current IS is fixed, then it is only needed to set the delta current ΔIP of the primary current IP for setting the maximum IPmax of the primary current IP to prevent the transformer 416 from magnetic saturation. It is shown by the equation EQ-10 that the delta current ΔIP of the primary current IP could be set by determining the device parameters of the resistors R1, R2 and R3, capacitor C1, inductor L1, and reference voltage Vtf, for example, by selecting the resistance of the resistor R3 to set the delta current ΔIP, and from the equation EQ-10 the resistor R3 has the resistance

$R 3 = Δ ⁢ ⁢ I P × L 1 × R 2 C 1 × V tf × ( R 1 + R 2 ) , [ EQ ⁢ - ⁢ 14 ]$
or by selecting the capacitance of the capacitor C1 to set the delta current ΔIP of the primary current IP, and from the equation EQ-10 the capacitor C1 has the capacitance

$C 1 = Δ ⁢ ⁢ I P × L 1 × R 2 V tf × R 3 × ( R 1 + R 2 ) . [ EQ ⁢ - ⁢ 15 ]$
Likewise, the secondary current IS of the transformer 416 has the maximum

$I S ⁢ max = N P N S × I P ⁢ max , [ EQ ⁢ - ⁢ 16 ]$
and together with the equation EQ-13, it is obtained the maximum of the secondary current

$I S ⁢ max = N P N S ⁢ Δ ⁢ ⁢ I P × I S ⁢ min . [ EQ ⁢ - ⁢ 17 ]$
Therefore, if the minimum ISmin of the secondary current IS is fixed, it could set the maximum ISmax of the secondary current IS by setting the delta current ΔIP of the primary current IP.

It is shown by the embodiment 400 that the delta current ΔIP of the primary current IP of the transformer 416 is determined by the resistors R1, R2 and R3, capacitor C1, inductor L1 and reference voltage Vtf, and therefore, it is easy to set the delta current ΔIP and the maximum IPmax of the primary current IP by selecting these parameters for not having the transformer 416 magnetically saturated.

FIG. 5 shows an application of another embodiment according to the present invention for a flash lamp module. In a capacitor charger 500, the basic architecture and the on-time decision circuit of the capacitor charger 400 shown in FIG. 4 are employed likewise, and the same numerals for those corresponding elements are also designated hereto. While to generate the signal Ss, a voltage generator 502 composed of resistors R4 and R5 is connected between the secondary voltage VL2 and ground GND to generate a voltage Vd2 varying with the secondary voltage VL2 as

$V d2 = V L2 × R 5 R 4 + R 5 . [ EQ ⁢ - ⁢ 18 ]$
A current source 504 determines a current IA2 according to the voltage Vd2. In the embodiment, the current source 504 includes a voltage-to-current converter that has a transconductive amplifier comprised of an operational amplifier 5042 and a transistor 5044 and a resistor R6 connected between the transistor 5044 and ground GND, in which the operational amplifier 5042 has a non-inverting input connected with the voltage Vd2, an inverting input connected to the resistor R6, and an output connected to the gate of the transistor 5044. Due to the virtual ground between the inputs of the operational amplifier 5042, the voltage drop across the resistor R6 is Vd2, and thus determines the current

$I A2 = V d2 R 6 . [ EQ ⁢ - ⁢ 19 ]$
From the equations EQ-18 and EQ-19, it is obtained the current

$I A2 = V L2 × R 5 R 4 + R 5 × 1 R 6 . [ EQ ⁢ - ⁢ 20 ]$
The current IA2 provided by the current source 504 is used as the reference current for a current mirror circuit 506 to generate a mirror current IB2 by mirroring the reference current IA2 supplied to the charge/discharge circuit 508. Since the reference current IA2 and the mirror current IB2 have the same magnitude, they are

$I B2 = I A2 = V L2 × R 5 R 4 + R 5 × 1 R 6 . [ EQ ⁢ - ⁢ 21 ]$
The charge/discharge circuit 508 includes a capacitor C3 and a transistor M3 serving as a switch shunt to the capacitor C3, and the transistor M3 is controlled by the off-time control logics 420. The current IB2 charges the capacitor C3 to generate a charged voltage VC2 that is compared with a reference voltage Vtf2 by a comparator 510 to generate a comparison signal Ss for the off-time control logics 420 to determine the off-time period

$T off = C 3 × V tf2 I B2 . [ EQ ⁢ - ⁢ 22 ]$
From the equations EQ-21 and EQ-22, it is obtained the off-time period

$T off = C 3 × V tf2 × R 6 × ( R 4 + R 5 ) V L2 × R 5 , [ EQ ⁢ - ⁢ 23 ]$
and the off-time period is also

$T off = L 2 × Δ ⁢ ⁢ I S V L2 . [ EQ ⁢ - ⁢ 24 ]$
By combining the equations EQ-23 and EQ-24, it is obtained the off-time period

$T off = L 21 × Δ ⁢ ⁢ I S V L2 = C 3 × V tf2 × R 6 × ( R 4 + R 5 ) V L2 × R 5 , [ EQ ⁢ - ⁢ 25 ]$
and thereby the resistance

$R 6 = Δ ⁢ ⁢ I S × L 2 × R 5 C 3 × V tf2 × ( R 4 + R 5 ) . [ EQ ⁢ - ⁢ 26 ]$
From the equation EQ-26, it is shown that the delta current ΔIS of the secondary current in the transformer 416 is proportional to the resistance of the resistor R6, and by which it could set the output current of the secondary winding L2 in the transformer 416 by setting the resistance of the resistor R6.

To control the capacitor chargers 400 and 500 or to switch the switch M1, there is no current sense resistor connected in series to the windings L1 or L2 of the transformer 416, and therefore no power loss is introduced by the current sense resistors. The delta current ΔIP of the primary current IP is easily to set and well controlled, and thus the transformer 416 could be prevented from magnetic saturation, thereby improving the efficiency thereof. The variation of the battery Vbat is also used to adjust the on-time period of the switch M1, thereby optimizing the operations of the capacitor chargers 400 and 500 adaptive to the varied input voltage Vbat, and the charging time and charging current are independent of the battery voltage Vbat.

While the present invention has been described in conjunction with preferred embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications and variations that fall within the spirit and scope thereof as set forth in the appended claims.

## Claims

1. A capacitor charger connected with an input voltage for generating an output voltage, the capacitor charger comprising:
a switch;
a transformer having a primary winding connected between the input voltage and the switch for generating a primary current flowing through the primary winding by switching the switch to thereby induce a secondary current flowing through a secondary winding of the transformer and a secondary voltage tapered from the secondary winding to further derive the output voltage, variation of the primary current in operable value remaining within a delta current parameter determined independent of the input voltage; and
a control apparatus connected to the switch for adjusting an on-time period for the switch adaptively in response to the input voltage.
a switch;
a transformer having a primary winding connected between the input voltage and the switch for generating a primary current flowing through the primary winding by switching the switch to thereby induce a secondary current flowing through a secondary winding of the transformer and a secondary voltage tapered from the secondary winding to further derive the output voltage, variation of the primary current in operable value remaining within a delta current parameter determined independent of the input voltage; and
a control apparatus connected to the switch for adjusting an on-time period for the switch adaptively in response to the input voltage.
2. The capacitor charger of claim 1, wherein the control apparatus comprises:
a voltage generator for providing a first voltage depending on the input voltage;
a current source for providing a reference current depending on the first voltage;
a current mirror for mirroring the reference current to thereby generate a minor current;
a charge/discharge circuit connected with the mirror current for generating a second voltage; and
a comparator for comparing the second voltage with a reference voltage to generate a comparison signal to further adjust the on-time period.
a voltage generator for providing a first voltage depending on the input voltage;
a current source for providing a reference current depending on the first voltage;
a current mirror for mirroring the reference current to thereby generate a minor current;
a charge/discharge circuit connected with the mirror current for generating a second voltage; and
a comparator for comparing the second voltage with a reference voltage to generate a comparison signal to further adjust the on-time period.
3. The capacitor charger of claim 2, wherein the voltage generator comprises a voltage divider connected with the input voltage for dividing the input voltage to thereby generate the first voltage.
4. The capacitor charger of claim 2, wherein the current source comprises;
a transistor having a drain for conducting the reference current;
an operational amplifier having a non-inverting input connected with the first voltage, an inverting input connected to a source of the transistor, and an output connected to a gate of the transistor; and
a resistor connected to the inverting input of the operational amplifier for setting the reference current.
a transistor having a drain for conducting the reference current;
an operational amplifier having a non-inverting input connected with the first voltage, an inverting input connected to a source of the transistor, and an output connected to a gate of the transistor; and
a resistor connected to the inverting input of the operational amplifier for setting the reference current.
5. The capacitor charger of claim 4, wherein the resistor has a resistance proportional to the delta current parameter determined for the primary current.
6. The capacitor charger of claim 2, wherein the charge discharge circuit comprises:
a capacitor for being charged by the mirror current to thereby generate the second voltage; and
a second switch shunt to the capacitor for resetting the capacitor.
a capacitor for being charged by the mirror current to thereby generate the second voltage; and
a second switch shunt to the capacitor for resetting the capacitor.
7. The capacitor charger of claim 6, wherein the capacitor has a capacitance proportional to the delta current parameter determined for the primary current.
8. The capacitor charger of claim 6, further comprising system control logics connected to the second switch for turning on the second switch to thereby reset the capacitor.
9. The capacitor charger of claim 2, further comprising on-time control logics connected with the comparison signal to adjust the on-time period.
10. The capacitor charger of claim 1, wherein the control apparatus comprises an off-time period generator connected to the secondary winding of the transformer for generating an off-time period for the switch in response to the secondary current.
11. The capacitor charger of claim 10, wherein the control apparatus further comprises off-time control logics connected to the off-time generator for determining the off-time period.
12. The capacitor charger of claim 1, wherein the control apparatus comprises:
a voltage generator for providing a first voltage depending on the secondary voltage;
a current source for providing a reference current depending on the first voltage;
a current mirror for mirroring the reference current to thereby generate a mirror current;
a charge discharge circuit connected with the mirror current for generating a second voltage; and
a comparator for comparing the second voltage with a reference voltage to generate a comparison signal to further determine an off-time period.
a voltage generator for providing a first voltage depending on the secondary voltage;
a current source for providing a reference current depending on the first voltage;
a current mirror for mirroring the reference current to thereby generate a mirror current;
a charge discharge circuit connected with the mirror current for generating a second voltage; and
a comparator for comparing the second voltage with a reference voltage to generate a comparison signal to further determine an off-time period.
13. The capacitor charger of claim 12, wherein the control apparatus further comprises off-time control logos connected with the comparison signal for determining the off-time period.
14. A control method for a capacitor charger having a primary winding of a transformer connected with an input voltage for generating an output voltage, the control method comprising the steps of:
switching a switch connected to the primary winding for generating a primary current flowing through the primary winding to thereby induce a secondary current flowing through a secondary winding of the transformer and a secondary voltage tapered from the secondary winding to further derive the output voltage;
maintaining variation of the primary current in operable value within a delta current parameter determined independent of the input voltage; and
adjusting an on-time period for the switch adaptively in response to the input voltage.
switching a switch connected to the primary winding for generating a primary current flowing through the primary winding to thereby induce a secondary current flowing through a secondary winding of the transformer and a secondary voltage tapered from the secondary winding to further derive the output voltage;
maintaining variation of the primary current in operable value within a delta current parameter determined independent of the input voltage; and
adjusting an on-time period for the switch adaptively in response to the input voltage.
15. The control method of claim 14, the step of adjusting an on- time period comprises the steps of:
generating a first voltage depending on the input voltage;
generating a reference current depending on the first voltage;
mirroring the reference current for generating a mirror current;
charging a capacitor with the mirror current for generating a second voltage; and
comparing the second voltage with a reference voltage for generating a comparison signal to further adjust the on-time period.
generating a first voltage depending on the input voltage;
generating a reference current depending on the first voltage;
mirroring the reference current for generating a mirror current;
charging a capacitor with the mirror current for generating a second voltage; and
comparing the second voltage with a reference voltage for generating a comparison signal to further adjust the on-time period.
16. The control method of claim 15, further comprising selecting a capacitance of the capacitor proportional to the delta current parameter determined for the primary current.
17. The control method of claim 15, wherein the step of generating a first voltage comprises dividing the input voltage for generating the first voltage.
18. The control method of claim 15, wherein the step of generating a reference current comprises generating the reference current proportional to the first voltage.
19. The control method of claim 15, further comprising resetting the capacitor.
20. The control method of claim 14, further comprising the steps of:
generating a first voltage depending on the secondary voltage;
generating a reference current depending on the first voltage;
mirroring the reference current for generating a mirror current;
charging a capacitor with the minor current for generating a second voltage; and
comparing the second voltage with a reference voltage for generating a comparison signal to further determine an off-time period for the switch.
generating a first voltage depending on the secondary voltage;
generating a reference current depending on the first voltage;
mirroring the reference current for generating a mirror current;
charging a capacitor with the minor current for generating a second voltage; and
comparing the second voltage with a reference voltage for generating a comparison signal to further determine an off-time period for the switch.