An RF switch design with adaptive DNW biasing in triple-well devices in 0.18-µm CMOS technology

Research paper by Sanghyun Woo, Hyoungsoo Kim, Hyun-woong Kim, Joy Laskar

Indexed on: 06 Apr '16Published on: 05 Apr '16Published in: Analog Integrated Circuits and Signal Processing


In this paper, we present a 1.9 GHz CMOS transmit/receive switch with the common mode shunt configuration and adaptive deep N-well (DNW) biasing techniques in order to achieve a high port-to-port isolation. The common mode shunt structure provides a low impedance shunt path to suppress the leakage in the off-switching state, and adaptive DNW biasing can cancel leakage from differential signals in the substrate. Experimental data shows that the proposed design achieves up to 8–10 dB higher port-to-port isolation than that of a conventional switch topology while maintaining insertion loss and power handling capability. The proposed switch is implemented in a standard 0.18-µm CMOS process and compared with the reference design in the TX and RX mode.