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Active leakage control in single-ended full-swing caches

Imported: 24 Feb '17 | Published: 24 Aug '04

Steven K. Hsu, Sanu K. Mathew, Ram Krishnamurthy

USPTO - Utility Patents

Abstract

A single-ended, full-swing dynamic cache having memory cells grouped into memory groups, where for each memory group one or more foot transistors connect to various memory cells within the memory group. Using a foot transistor reduces sub-threshold leakage current when the memory cells connected to the foot transistor are not being read.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a prior art cache.

FIG. 2 illustrates a portion of the prior art cache of FIG.

1.

FIG. 3 is an embodiment according to the present invention.

FIG. 4 illustrates a memory group belonging to the embodiment of FIG.

3.

FIG. 5 is another embodiment of the present invention utilizing multiple foot transistors for each memory group.

FIG. 6 illustrates a memory group belonging to the embodiment of FIG.

5.

Claims

1. A memory device comprising:

2. A memory device comprising a set of memory cells to store data and a foot transistor coupled to the set of memory cells, wherein each memory cell comprises:

3. The memory device as set forth in claim 2, further comprising:

4. A memory device, the memory device comprising:

5. The memory device as set forth in claim 4, further comprising:

6.The memory device as set forth in claim 5, the memory device having an evaluation phase and a pre-charge phase such that a read operation is performed only during an evaluation phase, the memory device further comprising:

7. The memory device as set forth in claim 4, the memory device having an evaluation phase and a pre-charge phase such that a read operation is performed only during an evaluation phase, the memory device further comprising:

8. A memory device comprising:

9. The memory device as set forth in claim 8, further comprising:

10. The memory device as set forth in claim 9, the memory device having an evaluation phase and a pre-charge phase such that a read operation is performed only during an evaluation phase, the memory device further comprising:

11. The memory device as set forth in claim 8, the memory device having an evaluation phase and a pre-charge phase such that a read operation is performed only during an evaluation phase, the memory device further comprising:

12. A memory device to read stored data addressable by an n-bit address, the memory device comprising:

13. The memory device as set forth in claim 12, further comprising:

14. The memory device as set forth in claim 13, wherein the decoder:

15. The memory device as set forth in claim 14, the memory device having an evaluation phase and a pre-charge phase where a read operation is performed during an evaluation phase, further comprising:

16. The memory device as set forth in claim 15, wherein each local bit line select signal keeps the corresponding pullup transistor ON during an evaluation phase only if no read operation is performed on the corresponding set of 2

n−m memory cells.

17. The memory device as set forth in claim 14, wherein the decoder comprises:

18. The memory device as set forth in claim 12, wherein k=0.