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A 132 Mb/s, 1bit 4224 M samples/s sub-sampling, low-complexity and energy-efficient BPSK transceiver for all-digital 3–5 GHz IR-UWB

Research paper by Jun Jiang, Ke Shao, Bo Lu, Hu Chen, Lingli Xia, Zhiliang Hong, Qian Chen

Indexed on: 24 Feb '13Published on: 24 Feb '13Published in: Analog Integrated Circuits and Signal Processing



Abstract

In this paper, a 3–5 GHz impulse radio ultra wideband BPSK transceiver is presented. A new all-digital architecture is applied in the proposed transceiver. The transceiver has no mixer and low complexity. The transmitter employs a RLC network response filter to achieve the adjustable pulse parameters, which includes pulse width, pulse bandwidth and pulse amplitude. Considering the low duty ratio, a proposed on/off output buffer in the transmitter is applied to save the power consumption. To simplify the receiver, the radio frequency input signal is amplified and sampled directly by a 1bit 4224 MHz sub-sampling ADC. The ADC comprises by 16 paralleled comparators for low power. Each comparator operates at 264 MHz and can be self-calibrated. The transceiver is implemented in SMIC 0.13 μm CMOS process at the supply of 1.2 V. The measured results show the adjustable parameters: the pulse amplitude is from 110 to 370 mV, the pulse width is from 900 to 1,600 ns and the pulse bandwidth is from 2.0 to 2.78 GHz. The data rate is 132 Mb/s between the transceiver. The transmitter and the receiver only consume 18.2 and 330 pJ/pulse, respectively. The receiver sensitivity is −75 dBm at the bit error rate of 10−3.