Indexed on: 07 Jul '12Published on: 07 Jul '12Published in: Analog Integrated Circuits and Signal Processing
A 1.2 V 8-bit single ended successive approximation register analog-to-digital converter (ADC) for long term evolution (LTE) system is implemented. A novel 5-bit resistor and 3-bit capacitor segment digital-to-analog converter is used to minimize the chip area and reduce the product cost. A rail-to-rail amplifier is used as the pre-amplifier of the comparator in order to obtain the full input swing and the adequate gain for low supply. The offset voltage of the comparator is below 2 mV from the Monte Carlo simulated results. The ring oscillator, current generator and bandgap are integrated into the ADC to satisfy multiple applications. The serial peripheral interface is used to adjust the sampling frequency and the key block’s bias current in order to change the dynamic and static power consumption to satisfy the different need in LTE’ modules. The design was fabricated in a 0.13 μm CMOS process with an area of 0.1 mm2 and a power of 1.2 mW. The measurement results show that the differential nonlinearity and integral nonlinearity of the proposed ADC are +0.11/−0.18 LSB and +0.8/−0.04 LSB, respectively. The spurious free dynamic range and signal-to-noise distortion ratio can get 53 and 43.3 dB, respectively.